Logic Decoding Research Articles

A pattern based instruction encoding technique for high performance architectures

In this paper we propose a new technique to reduce the program footprint and the instruction fetch latency in high performance architectures adopting long instructions in the memory. Our technique is based on an algorithm that factors long instructions into instruction patterns and encoded instructions, which contains no redundant data and it is stored into an I-cache. The instruction patterns look like a map to the decode logic to prepare the instruction to be executed in the execution stages. These patterns are stored into a new cache (P-cache). We evaluated this technique in a high performance architecture called 2D-VLIW through trace-driven experiments with MediaBench and SPEC programs. We compared the 2D-VLIW execution time performance before and after the encoding, and also with other encoding techniques implemented in computer architectures. Experimental results reveal that our encoding strategy provides a program execution time that is up to 69% better than EPIC.

Variability-Aware Design of Multilevel Logic Decoders for Nanoscale Crossbar Memories

The fabrication of crossbar memories with sublithographic features is expected to be feasible within several emerging technologies; in all of them, the nanowire (NW) decoder is a critical part since it bridges the sublithographic wires to the outer circuitry that is defined on the lithography scale. In this paper, we evaluate the addressing scheme of the decoder circuit for NW crossbar arrays, based on the existing technological solutions for threshold voltage differentiation of NW devices. This is equivalent to using a multivalued logic addressing scheme. With this approach, it is possible to reduce the decoder size and keep it defect tolerant. We formally define two types of multivalued codes (i.e., hot and reflexive codes), and we estimate their yield under high variability conditions. Multivalued hot decoders yield better area saving than <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">n</i> -ary reflexive codes, and under severe conditions, reflexive codes enable a nonvanishing part of the code space to randomly recover. The choice of the optimal combination of decoder type and logic level saves area up to 24%. We also show that the precision of the addressing voltages when a high variability affects the threshold voltages is a crucial parameter for the decoder design and permits large savings in memory area. Moreover, a precise knowledge about the variability level improves the design of memory decoders by giving the right optimal code.

A GENERALIZED ABFT TECHNIQUE USING A FAULT TOLERANT NEURAL NETWORK

In this paper, a measure of sensitivity is defined to evaluate fault tolerance of neural networks and we show that the sensitivity of a link is closely related to the amount of information passed through it. Based on this assumption, we prove that the distribution of output error caused by s-a-0 (stuck at 0) faults in an MLP network has a Gaussian distribution function. UDBP (Uniformly Distributed Back Propagation) algorithm is then introduced to minimize mean and variance of the output error. Then an MLP neural network trained with UDBP, contributes in an Algorithm-Based Fault Tolerant (ABFT) scheme to protect a nonlinear data process block. A systematic real convolution code guarantees that faults representing errors in the processed data will result in notable nonzero values in syndrome sequence. A majority logic decoder can now easily detect and correct single faults by observing the syndrome sequence. Simulation results demonstrating the error detection and correction behavior against random s-a-0 faults are presented too.

Self-orthogonal designs and codes from the symplectic groups [formula omitted] and [formula omitted

We determine self-orthogonal designs and self-orthogonal codes from the primitive representations of the projective symplectic groups S 4 ( 3 ) and S 4 ( 4 ) , respectively. We establish some properties of these codes and the nature of some classes of codewords. Some of the codes are optimal or near optimal for the given length and dimension. The dual codes of some designs and those of some complementary designs admit majority logic decoding.

Lightweight Error Correction Coding for System-Level Interconnects

Lightweight hierarchical error control coding (LHECC) is a new class of nonlinear block codes that is designed to increase noise immunity and decrease error rate for high-performance chip-to-chip and on-chip interconnects. LHECC is designed such that its corresponding encoder and decoder logic may be tightly integrated into compact, high-speed, and low-latency I/O interfaces. LHECC operates over a new channel technology called multi-bit differential signaling (MBDS). MBDS channels utilize a physical-layer channel code called N choose M (nCm) encoding, where each channel is restricted to a symbol set such that half of the bits in each symbol are set to one. These symbol sets have properties that are utilized by LHECC to achieve error correction capability while requiring low or zero relative information overhead. In addition, these codes may be designed such that the latency and size of the corresponding decoders are tightly bounded. The effectiveness of these codes is demonstrated by modeling error behavior of MBDS interconnects over a range of transmission rates and noise characteristics

Rate 2/3 modulation code for suppression of intrachannel nonlinear effects in high-speed optical transmission

An efficient approach in suppressing of intrachannel nonlinear effects using modulation codes is proposed. Significant Q-factor improvement ranging from 7–13 dB depending on modulation format, extinction ratio and number of spans is demonstrated. The encoder design is described, and sliding window decoding logic is given.

Realization of Multiple Valued Logic and Memory by Hybrid SETMOS Architecture

A novel complimentary metal-oxide-semiconductor (CMOS) single-electron transistor (SET) hybrid architecture, named SETMOS, is proposed, which offers Coulomb blockade oscillations and quasi-periodic negative differential resistance effects at much higher current level than the traditional SETs. The Coulomb blockade oscillation characteristics are exploited to realize the multiple valued (MV) literal gate and the periodic negative differential resistance behavior is utilized to implement capacitor-less multiple valued static random access memory (MV SRAM) cell. The SETMOS literal gate is then used to build up other MV logic building blocks, e.g., transmission gate, binary to MV logic encoder, and MV to binary logic decoder. Analytical SET model simulations are employed to verify the functionalities of the proposed MV logic and memory cells for quaternary logic systems. SETMOS MV architectures are found to be much faster and less temperature-sensitive than previously reported hybrid CMOS-SET based MV circuits.

MULTI-GHzSiGe BiCMOS FPGAs WITH NEW ARCHITECTURE AND NOVEL POWER MANAGEMENT TECHNIQUES

The availability of Silicon Germanium (SiGe) Heterojunction Bipolar Transistor (HBT) devices has opened a door for GHz Field Programmable Gate Arrays (FPGAs).1,2 The integration of high-speed SiGe HBTs and low-power CMOS gives a significant speed advantage to SiGe FPGAs over CMOS FPGAs. In the past, high static power consumption discouraged the pursuit of bipolar FPGAs from being scaled up significantly. This paper details new ideas to reduce power in designing high-speed SiGe BiCMOS FPGAs. The paper explains new methods to reduce circuitry and utilize a novel power management scheme to achieve a flexible trade-off between power consumption and circuit speed. In addition, new decoding logic is developed with shared address and data lines. A SiGe FPGA test chip based on the Xilinx 6200 architecture has been fabricated for demonstration.

A Robust Quadrature Decoding Logic and its FPGA Implementation for Measurement of Angular Motion using a Ring Laser Gyroscope

A ring laser gyroscope outputs an interference pattern that rotates at a rate proportional to the rotation rate of the body on which the gyroscope is strapped. The standard measurement setup for similar such systems consists of a pair of photo-detectors followed by wave shapers that convert the'rotating interference pattern into a pair of pulse trains in quadrature. The phase relation between the two pulse trains indicates the direction of rotation, and counting anyone of the pulse trains over a period of time gives a measure of the incremental motion. Commercially available optical encoder assemblies using similar quadrature-output sensors implement a sequence of noise filtering, quadrature phase detection and counting to measure incremental motion. Such designs have certain limitations in so far as their applicability is concerned. This paper documents these limitations briefly and proposes a novel design and its FPGA implementation of an improved digital noise filter and a high-resolution quadrature phase decoder for measurement of incremental motion based on the processing of the output of a ring laser gyroscope.

Soft-decision decoding of Reed–Muller codes based on simple multi-step SISO module

The paper proposes a new multi-step soft-decision decoding for the generic Reed–Muller (RM) code family, which is based on a simple multi-step soft-input soft-output (SISO) module and inherent merits of the RM codes. In an AWGN channel, the simulation results show that for RM codes of different code rates and lengths the introduced approach can offer pronounced performance gains over other soft-decision sub-optimal approaches and a conventional hard majority logic decoder. The results also indicate that the new algorithm can achieve a performance very close to that provided by a maximum likelihood decoder under the same conditions.

A Fast CMOS Optical Position Sensor With High Subpixel Resolution

This paper describes a novel architecture for an optical position sensor which has been implemented on a single chip using standard digital CMOS technology. The prototype device consists of 20/spl times/20 active pixels and two row and column parallel processing units with corresponding digital decoding logic. The image contour is extracted by means of distributed peak-detection, implemented at pixel level, followed by a digital extraction of the beam centroid position executed at row and column level. The sensor chip achieves up to 3000 frames/s with a position accuracy of 0.013 pixel and a total power consumption of 15 mW at 5 V.

Simulation study of the performance of ternary line codes under Viterbi decoding

The Viterbi decoding algorithm provides maximum likelihood decoding and has found widespread application since its introduction in 1967. It is currently the most widely used technique for the decoding of codes having a state system description, including the class of linear error correcting convolution codes. Contrary to this, it is still common practice to use combinational logic decoders for ternary line codes. These are nonlinear codes frequently used in metallic cable systems due to advantages such as efficient utilisation of bandwidth, and a DC-free power spectral density function. The authors investigate the behaviour of Viterbi decoding for the most important ternary line codes, and the coding gain that can be obtained by applying soft-decision decoding. The simplification of the Viterbi decoding implementation and the reduction in latency by shortening its survivor path length have also been investigated.

A 500-mb/s soft-output viterbi decoder

Two eight-state 7-bit soft-output Viterbi decoders matched to an EPR4 channel and a rate-8/9 convolutional code are implemented in a 0.18-μm CMOS technology. The throughput of the decoders is increased through architectural transformation of the add-compare-select recursion, with a small area overhead. The survivor-path decoding logic of a conventional Viterbi decoder register exchange is adapted to detect the two most likely paths. The 4-mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> chip has been verified to decode at 500 Mb/s with 1.8-V supply. These decoders can be used as constituent decoders for Turbo codes in high-performance applications requiring information rates that are very close to the Shannon limit.

Interactive built-in self-test compression for testing a system-on-a-chip

A methodology for test data compression and decompression in an interactive built-in self-test (iBIST) environment is presented. This methodology not only takes advantage of the strength of BIST in compression and test execution, but also overcomes BIST weaknesses by making it externally controllable. The data compression technique is realised in two steps. The first step consists of developing data to control the linear feedback self-register in generating patterns for random pattern resistant faults only. The second step uses a loss-less code to encode the control data and employs a loss-less and low-cost on-chip decodable coding scheme. A particular code was developed to illustrate the methodology; however, other codes may also be used within this environment. The proposed iBIST environment is well suited for compressing test data for the embedded logic cores in a system-on-a-chip. However, it can as well be used for component level testing. The experimental results obtained suggest that this compression scheme is comparable to the best technique available in the present literature. Furthermore, the decoding logic is estimated to be very low, e.g. less than 0.1% for cores of sizes of 100K gates or more. The architecture of test execution and its control including the decoding logic for the iBIST environment are also presented. The on- or off-chip first-in, first-out aspect of the architecture can ease the tight constraints of running a decoder synchronous to the external tester clock frequency.

Architectural support for efficient multicasting in irregular networks

Parallel computing on networks of workstations is fast becoming a cost-effective high-performance computing alternative to MPPs. Such a computing environment typically consists of processing nodes interconnected through a switch-based irregular network. Many of the problems that were solved for regular networks have to be solved anew for these systems. One such problem is that of efficient multicast communication. In this paper, we propose two broad categories of schemes for efficient multicasting in such irregular networks: network interface-based (NI-based) and switch-based. The NI-based multicasting schemes use the network interface of intermediate destinations for absorbing and retransmitting messages to other destinations in the multicast tree. In contrast, the switch-based multicasting schemes use hardware support for packet replication at the switches of the network and a concept known as multidestination routing to convey a multicast message from one source to multiple destinations. We first present alternative schemes for efficient multipacket forwarding at the NI and derive an optimal k-binomial multicast tree for multipacket NI-based multicast. We then propose two switch-based multicasting schemes that differ in the power of the encoding scheme and the complexity of the decoding logic at the switches. These multicasting schemes use path-based multidestination worms that can cover all nodes connected to switches along a valid unicast path and tree-based multidestination worms that can cover entire destination sets in a single phase using one worm, respectively. For each scheme, we describe the associated header encoding and decoding operation, the method for deriving multidestination worms that cover arbitrary multicast destination sets, and the multicasting scheme using the derived multidestination worms.

A third-generation SPARC V9 64-b microprocessor

This quad-issue processor achieves 1-GHz operation through improved dynamic circuit techniques in critical paths and a more extensive on-chip memory system which scales in both bandwidth and latency. Critical logic paths use domino, delayed clocked domino, and logic embedded in dynamic flip-flops for minimum delay. A 64-KB sum-addressed memory data cache combines the address offset add with the cache decode, allowing the average memory latency to scale by more than the clock ratio. Memory bandwidth is improved by using wave pipelined SRAM designs for on-chip caches and a write cache for store traffic. Memory power is controlled without increased latency by use of delayed-reset logic decoders. The chip operates at 1000 MHz and dissipates less than 80 W from a 1.6-V supply. It contains 23 million transistors (12 million in RAM cells) on a 244 mm/sup 2/ die.

Binary codes derived from the Hoffman-Singleton and Higman-Sims graphs

Some binary linear codes of length 50 and 100 are constructed using the adjacency matrices of the Hoffman-Singleton graph and the Higman-Sims graph, Some of the codes are optimal or nearly optimal for the given length and dimension. The dual codes admit majority logic decoding.

A low voltage SRAM for embedded applications

A 4-kb SRAM design is presented with functionality of 12 MHz at a supply voltage of 0.9 V with an r.m.s. run power (1 MHz) of 18 /spl mu/W. The circuit operates at maximum frequency of 40 MHz at a supply voltage of 1.6 V with an rms run power (1 MHz) of 64 /spl mu/W. The design utilizes a subblocked array architecture as well as selective use of NOR/NAND-based decode logic. The sense amplifier design is a low voltage, glitch-free design to conserve power.

A combinatorial consideration of the error‐correcting capability of difference‐set cyclic codes

AbstractThis paper discusses a theoretical method for estimating the error‐correcting capability (ECC) of difference‐set cyclic codes (DSCCs). DSCCs can be decoded by using majority logic decoding (MLD); however, variable threshold decoding (VTD) is often employed to improve performance. A combinatorial consideration of the ECC using MLD first must define the probability of failure to correct errors at each reference bit. Both the perfect recovery rate and the discrete probability density (DPD) of residual errors after an MLD processing are then calculated. the ECC achieved by using VTD equipped with two concatenated MLDs is estimated based on the DPD. the numerical estimations of the ECC are examined by comparing them with conventional computer simulation results. These results show that the calculated values conform well to the simulation values. the proposed method can be applied efficiently to test both error‐correcting chips and the design of the built‐in self‐test circuit for them. Results can also be applied to estimate the performances of new super‐long codes, to which little attention has been paid so far.

Algorithms for threshold level selection and decoder logic design in decision-aided symbol-by-symbol data receivers for magnetic recording applications

Symbol-by-symbol receivers comprise an important class of data receivers in digital magnetic recording applications. In systems where intersymbol interference (ISI) is high, these systems often use decision-aided decoding methods. A typical system employs threshold level detection followed by decoding logic. This paper presents an algorithm for selecting decoder threshold level settings and for generating the truth table for the decoding logic. By making use of all information available to the receiver, it is demonstrated that considerable reduction in the number of threshold levels required can be achieved in systems where the data encoding obeys run length limit constraints. It is also shown that selection of decode timing reference may have considerable influence on the number of threshold levels required. Application of the algorithm is demonstrated for several partial response signaling channels. A brief discussion is given on the similarities between the structure proposed by this paper and standard decision feedback equalizers.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>