Decision Feedback Research Articles

Decision Feedback Scheme with Criterion LR+Th for the Ensemble of Linear Block Codes

A decision criterion called LR+Th for decision feedback scheme was proposed by Hashimoto. Though Forney’s decision criterion (FR) is optimal and meets the Neyman-Pearson’s lemma, LR+Th is suboptimal. However, the error exponent of LR+Th is shown to be asymptotically equivalent to that of FR by random coding arguments for block codes. In this paper, applying the technique of DS2 bound, we derive an upper bound for the error probability of LR+Th with the ensemble of linear block codes. It elucidates the relation between the random coding exponents of block codes and those of linear block codes.

A 36 Gb/s wireline receiver with adaptive CTLE and 1-tap speculative DFE in 0.13 µm BiCMOS technology

This paper presents a 36 Gb/s receiver equalizer including an adaptive continuous time linear equalizer (CTLE), which is based on slope detection and a half-rate speculative decision feedback equalizer (DFE) in 0.13 µm BiCMOS technology for high speed serial link. The CTLE with middle frequency compensation can not only adjust the ratio of high frequency and low frequency components adaptively, but also provide a small amount of equalization to middle frequency range. A half-rate speculative DFE, which is connected to the back of the CTLE, can satisfy the time constraints and eliminate the residual inter-symbol interference. The chip area including pads is about 1.2 mm2 and the power consumption is about 750 mW under 3.3 V power supply. Measurement results show that the receiver chip can effectively equalize 24 dB loss at Nyquist frequency and a clear eye diagram can be captured at 36 Gb/s.

A 112–134-Gb/s PAM4 Receiver Using a 36-Way Dual-Comparator TI-SAR ADC in 7-nm FinFET

This letter describes a 112–134-Gb/s PAM-4 wireline receiver (Rx) designed and fabricated in 7-nm CMOS FinFET technology. The Rx includes a T-Coil-assisted on-die termination (ODT), an adaptable continuous-time linear equalizer (ACTLE), a time-interleaved ADC (TI-ADC), clock generation, clock distribution, feed-forward equalizer (FFE), decision feedback equalizer (DFE), and calibration. The TI-ADC is implemented as a 56–67-GSa/s, 36-way arrangement of dual-comparator SAR ADCs (SAR subADCs). The Rx achieves BER better than 1e-4 for a data rate as high as 127 Gb/s, with 3.2e-4 BER at 134.4 Gb/s, over a 15-dB die-to-die loss channel and achieves 3e-6 BER over a 33-dB die-to-die channel loss at 28-GHz Nyquist while consuming 5.1 pJ/b of power, excluding DSP power.

RESEARCH ON DYNAMIC SCHEDULING DECISION ALGORITHM IN MIMIC DEFENSE

In this paper, a dynamic scheduling decision algorithm based on mimic defense is proposed. According to the output of the decision feedback executor, different executors are selected by the scheduler to realize the feedback security defense mechanism. Firstly, the scheduling algorithm is used to dynamically select the executor set in the execution pool to reduce overhead and improve security. And then the output of the execution set is determined by the improved majority decision algorithm based on the reliability factor. Finally, the simulation results show that the dynamic feedback scheduling algorithm can effectively improve the security of the system.

A Novel Decision Feedback Equalization Structure for Nonlinear High-Speed Links

As the degree of nonlinearity in high-speed links becomes more and more serious, traditional decision feedback equalization (DFE) which is based on linear time-invariant assumption can no longer eliminate the inter-symbol interference effectively. In this paper, the shortcomings of traditional DFE structure for nonlinear high-speed links are first analyzed. Then, the multi-bit response (MBR) method is proposed to accurately construct the bit stream responses of the nonlinear high-speed links. Lastly, a novel DFE structure based on the MBR method is presented to improve the signal quality of the nonlinear high-speed links. The accuracy of the proposed method is verified by the simulation based on a nonlinear high-speed link model. Compared with traditional DFE, the proposed DFE structure can significantly improve the signal quality of the nonlinear high-speed links. As the degree of nonlinearity increases, the advantage of the proposed DFE becomes more prominent.

A Body Channel Communication Technique Utilizing Decision Feedback Equalization

This article presents the body channel communication technique that first adopts decision feedback equalisation. For the first time, we characterised post-cursor intersymbol interference of a single-bit pulse response of a human body channel for decision feedback equalisation achieving the first body channel communication faster than 100 Mb/s. In the proposed technique, an 8-tap decision feedback equaliser is utilised at the receiver to compensate for intersymbol interference of the body channel. The experimental results show that the proposed prototype transceiver achieved the highest data rates of 150 Mb/s and 10 Mb/s along 20-cm and about 100-cm body channels, respectively. Compared to the previous best result measured for the same body-channel distance of about 100 cm, the data rate is improved by ten times, showing that the proposed technique can significantly increase the speed of body channel communication.

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

A 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 is presented in 10-nm class CMOS technology. Various functions and circuits' techniques are newly adopted to improve performance and power consumption compared with DDR4 SDRAM. First, to realize two times higher speed than DDR4, the injection-locked oscillator (ILO) delay locked loop (DLL) is adopted for the low jitter high-speed performance. The proposed DLL with phase rotator (PR) and ILO allows to minimize the clock tree of DRAM, lowering skew and jitter in the DRAM internal clock path. Second, for the high-speed write operation, DQS gate opening control and write leveling are very important to minimize the turnaround time of DRAM, and thus new sequence and logic for the write-level training are introduced in this article. Third, to maximize the data valid window of read DQs, duty cycle adjustable serialize circuit methods are proposed. Finally, to improve the interface speed, the decision feedback equalization (DFE) and feedforward equalization (FFE) are adopted to Rx and Tx, respectively. By implementing all the items mentioned earlier, the 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 achieved 6.4-Gb/s/pin performance at 1.05-V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , with its power bandwidth efficiency 30% higher than that of DDR4.

A new flip-flop based on discrete-time parametric amplifier

This paper introduces a low power flip-flop based on the discrete-time parametric amplifier, with improved rise (fall) time, setup-time, hold-time, and area. Post-layout simulation result of the proposed flip-flop in a 180 nm CMOS technology with 3.33 GHz frequency illustrates about 21% of the power consumed by CML flip-flop and about 30% improvement in the clock-to-q delay. Also, the simulation shows improved rise (fall) time, lower data-to-q delay compared to dynamic CML and Footless flip-flop, lower area than Charge Steering flip-flops without the need for additional return-to-zero to non-return-to-zero conversion circuitry. When using this flip-flop as a slicer in a decision feedback equalizer (DFE) circuit of a serial link receiver of 1 m Nelco backplane channel, the post-layout simulation results show that the DFE circuit based on the parametric flip-flop has about 50% improvement of power consumption in comparison with the conventional CML DFE circuit in identical conditions.

A 7.8-Gb/s 2.9-pJ/b Single-Ended Receiver With 20-Tap DFE for Highly Reflective Channels

For the first time, we prove that 7.8-Gb/s single-ended signaling through a highly reflective channel is feasible at low energy cost by an energy-efficient many-tap decision feedback equalization (DFE) receiver (RX). The reported data rate of 7.8 Gb/s is the fastest data rate that has been achieved through a single-ended highly reflective channel that has more than five taps of postcursor reflective intersymbol interference. Compared with the prior arts, the target multidrop has the most in-band notches: ten notches. To compensate for large reflection by many notches, the RX exploits the DFE with the largest tap count of 20 that has been never used in single-ended signaling before. Low-power circuit techniques such as a current-integrating summer and double-tail sense amplifiers were adequately adopted and engineered to reduce large power dissipation by many taps. The RX was fabricated in a 65-nm CMOS technology and occupies only 0.014 mm2. The energy efficiency was measured to be only 2.9 pJ/b at 7.8 Gb/s with 0.9-V supply, proving that fast single-ended signaling through a highly reflective channel is feasible at low energy cost by many-tap DFE if low-power circuit techniques are adequately applied. The horizontal and vertical eye sizes were measured to be 0.12 UI and 34 mV, respectively, at a bit error rate of <10−12.

An Energy Dynamic Control Algorithm Based on Reinforcement Learning for Data Centers

In recent years, how to use renewable energy to reduce the energy cost of internet data center (IDC) has been an urgent problem to be solved. More and more solutions are beginning to consider machine learning, but many of the existing methods need to take advantage of some future information, which is difficult to obtain in the actual operation process. In this paper, we focus on reducing the energy cost of IDC by controlling the energy flow of renewable energy without any future information. we propose an efficient energy dynamic control algorithm based on the theory of reinforcement learning, which approximates the optimal solution by learning the feedback of historical control decisions. For the purpose of avoiding overestimation, improving the convergence ability of the algorithm, we use the double [Formula: see text]-method to further optimize. The extensive experimental results show that our algorithm can on average save the energy cost by 18.3% and reduce the rate of grid intervention by 26.2% compared with other algorithms, and thus has good application prospects.

Synchronization Error Robust Transceivers for Molecular Communication

Molecular communication has been proposed as a signaling mechanism to enable communication between nano-machines via molecular diffusion. Precise synchronization of transmitters and receivers is particularly challenging in diffusive molecular communication environments due to the propagation characteristics. To mitigate sensitivity to synchronization errors, a decision feedback equalizer, sequential probability ratio test (DFE-SPRT) based receiver and an approximate maximum-likelihood delay estimator are derived. The performance of the delay estimator is shown to be close to a Cramer-Rao bound at low transmission rates. Numerical results show that the DFE-SPRT makes a decision well before the full symbol interval is exhausted; the desirability of this effect is theoretically justified through the adaptation of the analysis of the log-loss function for mismatched Poisson random variables. Performance bounds on the DFE-SPRT are employed to design optimized modulation for the mis-synchronized communication channel. The proposed receiver and modulation designs achieve strongly improved asynchronous detection performance for the same data rate relative to recently proposed receiver designs that also exploit decision feedback.

Adaptive Activity-Aware Iterative Detection for Massive Machine-Type Communications

This letter studies the uplink of grant-free low data-rate massive machine-to-machine communications (mMTC) where devices are only active sporadically, which requires a joint activity and data detection at the receiver. We develop an adaptive decision feedback detector along with an $l_{0}$ -norm regularized activity-aware recursive least-squares algorithm that only require pilot symbols. An iterative detection and decoding scheme based on low-density parity-check (LDPC) is also devised for signal detection in mMTC. Simulations show the performance of the proposed approaches against existing schemes.

137 Gb/s PAM-4 Transmissions at 850 nm over 40 cm Optical Backplane with 25 G Devices with Improved Neural Network-Based Equalization

An improved neural network-based equalization method is proposed and experimentally demonstrated. The up-to-137 Gb/s transmission of four level pulse amplitude modulation (PAM-4) signals with 25 G class 850 nm optical devices is achieved over an in-house fabricated 40 cm optical backplane. An in-depth investigation is conducted regarding the impact of delayed taps and spans on equalization performance. A performance comparison of the proposed method with the traditional maximum likelihood sequence estimation (MLSE) and decision feedback equalization (DFE) is also undertaken. For the bit rate from 80 to 100 Gb/s, the proposed method achieves an adopted hard-decision forward error correction (HD-FEC) requirement at a received optical power (RoP) of −9 and −8 dBm, while DFE and MLSE cannot meet the HD-FEC requirement. When the bit rate increases from 120 to 137 Gb/s, the proposed equalization method still successfully maintains the acceptable system performance at an RoP of −4 and −2.5 dBm. Furthermore, the specific bit error rate (BER) performances for varied maximum achievable bit rate under different RoPs by applying MLSE and the proposed method are also analyzed. This provides an important potential solution to realize the future data centers.

Adaptive Equalization for Dispersion Mitigation in Multi-Channel Optical Communication Networks

Optical communication networks (OCNs) provide promising and cost-effective support for the ultra-fast broadband solutions, thus enabling them to address the ever growing demands of telecommunication industry such as high capacity and end users’ data rate. OCNs are used in both wired and wireless access networks as they offer many advantages over conventional copper wire transmission such as low power consumption, low cost, ultra-high bandwidth, and high transmission rates. Channel effects caused by light propagation through the fiber limits the performance, hence the data rate of the overall transmission. To achieve the maximum performance gain in terms of transmission rate through the OCN, an optical downlink system is investigated in this paper using feed forward equalizer (FFE) along with decision feedback equalizer (DFE). The simulation results show that the proposed technique plays a key role in dispersion mitigation in multi-channel optical transmission to uphold multi-Gb/s transmission. Moreover, bit error rate (BER) and quality factor (Q-factor) below 10 − 5 and above 5, respectively, are achieved with electrical domain equalizers for the OCN in the presence of multiple distortion effects showing the effectiveness of the proposed adaptive equalization techniques.

A 36-Gb/s Adaptive Baud-Rate CDR With CTLE and 1-Tap DFE in 28-nm CMOS

This letter presents the design details of a 36-Gb/s adaptive baud-rate clock and data recovery circuit (CDR) with continuous-time linear equalizers and 1-tap decision feedback equalizer (DFE) fabricated in 28-nm CMOS. The proposed on-chip adaptation engine is tailored to a baud-rate CDR, where the front-end comparators are shared between the DFE and the PD to save power. The adaptive scheme is demonstrated on a baud-rate CDR testchip that has sampler-based front-end equalization which is more suitable for low-power, short reach, applications instead of a power intensive ADC/DSP-based receiver approach that is usually meant for long-reach (LR) links. This testchip was validated with 34–36 Gb/s random input data (PRBS31 & 7) with channel loss of 15.05–18.25 dB at Nyquist. The total power consumption is measured to be 106.3 mW, equivalent to an FOM of 3.04 pJ/bit at 35 Gb/s.

Bridging the Gap Between MMSE-DFE and Optimal Detection of MIMO Systems

In this paper, we propose a novel low-complexity, near-optimal soft-input soft-output detector for $\text {N}\times \text {M}$ multiple-input multiple-output (MIMO) systems. Our algorithm is based on the combination of minimum mean square error decision feedback equalization (MMSE-DFE) and conditional optimization. In a round-robin fashion, one symbol is detected using exhaustive search in such a way that all $\text {N}\times (\text {M}-1)$ submatrices of the baseband channel matrix are considered and the one with the best metric is chosen. This search over all columns of the channel matrix, which can be performed in parallel, has the advantages of improving the performance of the hard-output version of the detector, and refining the list of candidates for efficient implementation of the soft-output detector for MIMO systems with error correcting codes. In particular, it is shown that the error performance of the soft-output system is comparable to that of the list sphere decoder (LSD) but with much smaller list size, and hence smaller complexity than the latter. We also analyze the performance and complexity of the proposed algorithm and discuss different techniques to further reduce its complexity without affecting the performance. Finally, the obtained theoretical results are validated via simulations.

An adaptive QR-based energy efficient signal detection scheme in MIMO-OFDM systems

In this paper, an adaptive QR-based energy efficient low complexity signal detection scheme in multiple input multiple output-orthogonal frequency division multiplexing (MIMO-OFDM) systems with nearly optimal error performance is proposed for solving the disadvantage of path elimination QR decomposition-M algorithm (PEQRD-M). For minimizing the loss of error performance, the proposed scheme uses suboptimal PEQRD- M, and hybrid PEQRD- M and lattice reduction-aided decision feedback equalizer (LR-aided DFE) adaptively by using channel state. The proposed scheme selects the signal detection scheme adaptively by calculating the condition number of wireless channel. The proposed scheme uses PEQRD- M when the channel state is poor where its condition number is high, and reversely uses the hybrid PEQRD-M and LR-aided DFE when the channel state is favorable where its condition number is low. The simulation results show that the proposed scheme has nearly the same error performance as PEQRD- M and low complexity at low signal to noise ratio (SNR).

Sequence-Coded Multilevel Signaling for High-Speed Interface

This article describes a 32-Gb/s sequence-coded link. We introduce a self-converging and reduced state trellis structure that can be configured as pulse amplitude modulation (PAM)-4 or PAM-5. Exploiting the channel ISI, the transmitter creates a trellis structure by independently setting the tap weights and skew between the MSB and LSB digital-to-analog converters (DACs). The receiver, including the digital decoder, consumes only 52 mW. The implemented transceiver in 28-nm fully depleted silicon-on-insulator (FDSOI) operates up to 32 Gb/s with 2.6-pJ/bit efficiency compensating up to 30-dB loss. Sequence-coded PAM-5 reduces hardware complexity by 66% compared to one-tap loop-unrolled decision feedback equalization (DFE) for similar performance. Compared to conventional PAM-4, the proposed sequence-coded PAM-4 link provides 4-dB SNR gain for a 10-dB loss channel and 6-dB SNR gain for 30-dB loss channel with 12.5% bandwidth overhead.

Optimization of Band-Limited DSP-Aided 25 and 50 Gb/s PON Using 10G-Class DML and APD

The increasing demand for network capacity is driving the development of next-generation high-speed Passive Optical Networks (PON) supporting 25 and 50 Gbps. One solution to reduce transceiver cost is reusing the 10G-class optical transmitter (including Directly Modulated Lasers, DML, in O-band) and receiver components in combination with Digital Signal Processing (DSP) techniques to compensate for bandwidth limitations. In this article, by means of both a set of laboratory experiments and a metropolitan field demonstrator, we discuss practical PON solutions at 25 and 50 Gbps per wavelength and per direction. In terms of modulation formats, we compare 2-level pulse amplitude modulation (PAM-2), 4-level PAM (PAM-4), and electrical duobinary (EDB) modulation formats, with feed-forward (FFE) and decision-feedback (DFE) adaptive equalizer at the receiver side. The novelty of our article is manifold. First, we present an optimization in terms of optical receiver band requirements for the 50 Gbps transmission. We show, by means of experimental measurements and numerical simulations, the minimum required bandwidth for DML laser and APD receiver (with appropriate DSP techniques) to realize next generation 25 and 50 Gbps PON transceivers. Second, we discuss also the upstream point of view, with a specific focus on DSP, and in particular, we propose an experimental solution based on a burst mode receiver with memory-aided DSP technique, together with a novel DSP approach to overcome the typical AC coupling distortion due to the burst mode scenario. Finally, we show a coexistence experiment between XGS-PON and 25 Gbps PON on an installed metropolitan field trial.

Sign 3 ‐LMS data‐transition decision feedback equaliser

This study presents an adaptive data-transition decision feedback equaliser (DT-DFE) with a sign3 least-mean-square (LMS) tap adaptation. Commonly used data-state (DS) DFE suffers from reduced vertical eye-opening when consecutive 1's or 0's are encountered. The proposed DT-DFE performs DFE only when a data transition is detected. It boosts the eye-opening of the high-frequency components of data without attenuating the low-frequency components of data whereas DS-DFE boosts the eye-opening of the high-frequency components of data at the expense of the attenuated low-frequency components of data. The reference voltages of DS-DFE is tap-dependent whereas those of DT-DFE are tap-independent and are obtained by conveying consecutive 1's and 0's to the channel in a training phase. The proposed DT-DFE utilises loop unrolling to detect the occurrence of data transition. The performance of the proposed DT-DFE is compared with that of DS-DFE using two 5 Gbps backplane serial links designed in a TSMC 65 nm CMOS technology. Simulation results demonstrate that the eye-opening of the link with DT-DFE is 1.54 times that with DS-DFE. The vertical eye-opening of the link with DT-DFE activating tap adaptation on two consecutive state transitions of opposite polarities is 1.2 times that that activates tap adaptation on single state transition. The proposed DT-DFE is less sensitive to process uncertainty whereas DS-DFE is prone to process uncertainty with severely deteriorating performance.