Abstract
This article describes a 32-Gb/s sequence-coded link. We introduce a self-converging and reduced state trellis structure that can be configured as pulse amplitude modulation (PAM)-4 or PAM-5. Exploiting the channel ISI, the transmitter creates a trellis structure by independently setting the tap weights and skew between the MSB and LSB digital-to-analog converters (DACs). The receiver, including the digital decoder, consumes only 52 mW. The implemented transceiver in 28-nm fully depleted silicon-on-insulator (FDSOI) operates up to 32 Gb/s with 2.6-pJ/bit efficiency compensating up to 30-dB loss. Sequence-coded PAM-5 reduces hardware complexity by 66% compared to one-tap loop-unrolled decision feedback equalization (DFE) for similar performance. Compared to conventional PAM-4, the proposed sequence-coded PAM-4 link provides 4-dB SNR gain for a 10-dB loss channel and 6-dB SNR gain for 30-dB loss channel with 12.5% bandwidth overhead.
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