DDR SDRAM Research Articles

FPGA-Based Numerical Simulation of the Chaotic Synchronization of Chua Circuits

The objective of this work was to design and implement a system based on reconfigurable hardware as a study tool for the synchronization of chaotic circuits. Mathematical models were established for one circuit, two synchronized, and multiple synchronized Chua circuits. An ordinary differential equation solver was developed applying Euler’s method using the Verilog hardware description language and synthesized on a Spartan 3E FPGA (Field-Programmable Gate Array) equipped with a 32-bit RISC processor, 64 MB of DDR SDRAM, and 4 Mb of PROM. With a step size of 0.005 and a total of 10,000 iterations, the state equations for one and three Chua circuits were solved at a time of 0.2 ms and a frequency of 50 Mhz. The logical resources used by the system did not exceed 4%. To verify the operation, a numerical simulation was carried out using the Octave V9.1.0 calculation software on an Intel(R) Core i7-9750H CPU 2.59 GHz computer, obtaining the same results but in a time of 493 ms and 3.177 s for one and three circuits, respectively.

Impact of Particle Radiation and Temperature on the Retention Time of DDR4 SDRAM Cells

Impact of Particle Radiation and Temperature on the Retention Time of DDR4 SDRAM Cells

A 14 GHZ DELAY LOCKED LOOP WITH MINIMIZED PERIOD DELAY ERROR AND WORST 1.5% DUTY CYCLE ERROR

In many applications, the Delay Locked Loop (DLL) is used to improve the timing margin for better performance of the synchronous system. A precise 50′ duty ratio of the clock signal is essential to the DDR SDRAM, which needs both the rising edge and the falling edge of the clock to sample the data. The duty mismatch of the output clock in the DLL may be caused by the duty error of the external input clock or by the common mode voltage offset in the voltage-controlled delay line (VCDL). Many studies have presented the duty cycle corrector (DCC) to reduce the duty mismatch of the clock. This paper proposes a high-frequency DLL that generates multiplate clocks with a wide frequency range. The object of this research is to have +-1.5% duty cycle error at the output clock and, in locked state, less than 2% of clock period delay between 0- and 360-degree phases (delay error). This generator produces 8 phases at 14 GHz.

Online Application Guidance for Heterogeneous Memory Systems

As scaling of conventional memory devices has stalled, many high-end computing systems have begun to incorporate alternative memory technologies to meet performance goals. Since these technologies present distinct advantages and tradeoffs compared to conventional DDR* SDRAM, such as higher bandwidth with lower capacity or vice versa, they are typically packaged alongside conventional SDRAM in a heterogeneous memory architecture. To utilize the different types of memory efficiently, new data management strategies are needed to match application usage to the best available memory technology. However, current proposals for managing heterogeneous memories are limited, because they either (1) do not consider high-level application behavior when assigning data to different types of memory or (2) require separate program execution (with a representative input) to collect information about how the application uses memory resources. This work presents a new data management toolset to address the limitations of existing approaches for managing complex memories. It extends the application runtime layer with automated monitoring and management routines that assign application data to the best tier of memory based on previous usage, without any need for source code modification or a separate profiling run. It evaluates this approach on a state-of-the-art server platform with both conventional DDR4 SDRAM and non-volatile Intel Optane DC memory, using both memory-intensive high-performance computing (HPC) applications as well as standard benchmarks. Overall, the results show that this approach improves program performance significantly compared to a standard unguided approach across a variety of workloads and system configurations. The HPC applications exhibit the largest benefits, with speedups ranging from 1.4× to 7× in the best cases. Additionally, we show that this approach achieves similar performance as a comparable offline profiling-based approach after a short startup period, without requiring separate program execution or offline analysis steps.

Multi-source Intelligent Management System of College Snow and Ice Teaching Based on Cloud Platform

The conventional college snow and ice teaching multi-source resource intelligent management system has the problem of incomplete software resource analysis function, which leads to high CPU usage of system. A cloud platform based college snow and ice teaching multi-source resource intelligent management system is designed. Hardware part: record the state of the pins when the register is reset, account for the data bit width and storage capacity of DDR2 SDRAM memory, and optimise the data storage module; Part of the software: obtain ice and snow sports course objectives in colleges and universities, rationally organise the course organization form, optimise the intelligent management mode of teaching multi-source resources by using the cloud platform, support online browsing of various text resources, set relevant parameters to construct various random modification operations, and design the software resource analysis function with the knowledge fusion algorithm. Experimental results: The average CPU usage of the multi-source intelligent resource management system for snow and ice teaching in colleges and universities in this paper and the other two systems is 34.257%, 47.458%, 53.578%. Experimental results show that the performance of multi-source intelligent resource management system for snow and ice teaching in colleges and universities has been significantly improved after making full use of cloud platform.

Implementation of a Real-Time Vision Based Vehicle License Plate Recognition System

Abstract: Automatic Number-plate recognition is a technology that uses visual cues in images to read vehicle registration plates to create vehicle location data. It can use closed television, traffic law cameras, or cameras designed for work. ANPR is used by police around the world for legal purposes, including checking whether a vehicle is registered or licensed. It is also used for the collection of electronic toll on individual toll roads and as a catalyst for traffic mobility, for example by highway agencies. The automatic number plate recognition can be used to store camera-captured images and text from the license plate, another configurable to save the driver's image. Systems usually use infrared light to allow the camera to take pictures at any time of the day or night. An Intelligent Vehicle Safety recording system that uses image processing usually requires a large internal memory register or DDR SDRAM (Random Double Data Access) for temporary video and photos. But these processes often increase the complexity of hardware and software. In this program, we propose a VLSI implementation for a photographic route departure system. It is not only a calculation of line melting and discrimination outside the line, but also a real-time analysis of car tires on the left and right side of the track marker with a video image, and then judge the car offsets phenomenon. Keywords: ANPR, Artificial Intelligence, Government Tracking, Security etc.

An Efficient Dual-Channel Data Storage and Access Method for Spaceborne Synthetic Aperture Radar Real-Time Processing

With the development of remote sensing technology and very large-scale integrated circuit (VLSI) technology, the real-time processing of spaceborne Synthetic Aperture Radar (SAR) has greatly improved the ability of Earth observation. However, the characteristics of external memory have led to matrix transposition becoming a technical bottleneck that limits the real-time performance of the SAR imaging system. In order to solve this problem, this paper combines the optimized data mapping method and reasonable hardware architecture to implement a data controller based on the Field-Programmable Gate Array (FPGA). First of all, this paper proposes an optimized dual-channel data storage and access method, so that the two-dimensional data access efficiency can be improved. Then, a hardware architecture is designed with register manager, simplified address generator and dual-channel Double-Data-Rate Three Synchronous Dynamic Random-Access Memory (DDR3 SDRAM) access mode. Finally, the proposed data controller is implemented on the Xilinx XC7VX690T FPGA chip. The experimental results show that the reading efficiency of the data controller proposed is 80% both in the range direction and azimuth direction, and the writing efficiency is 66% both in the range direction and azimuth direction. The results of a comparison with the recent implementations show that the proposed data controller has a higher data bandwidth, is more flexible in its design, and is suitable for use in spaceborne scenarios.

Design of DDR3 SDRAM read-write controller based on FPGA

In order to flexibly adjust the frame delay of real-time image acquisition by high-resolution cameras, which is based on optical fiber communication protocol, and facilitate subsequent control, this article uses MT41J128M16JT-125IT DDR3 SDRAM of Mircon company to cache image data. And based on the MIG controller that comes with Xilinx Vivado development tool for continuous read and write control, the results show that when the camera system is designed at 2fps and the system clock is 50Mhz, the system data bandwidth is 2.2Gbps. The selected DDR3 chip has a bandwidth of 6.25Gbps, which can meet the real-time transmission requirements of the design system.

Особенности интерфейса устройства тестового диагностирования памяти DDR SDRAM

The I/О synchronization scheme plays an important role in achieving maximum speed and reliability of data transmission during memory operation. This paper presents the interface architecture of the DDR SDRAM test diagnostic device. It was demonstrated that the proposed interface components provide the formation of a bidirectional synchro signal for gating written and read data when performing test diagnostics of chips and DDR SDRAM memory devices. Compared to traditional methods, the proposed interface components were made on integrated electronic elements, which reduced the size and power consumption. It has been established that the use of a multiphase synchronization system to implement the interface eliminated the use of delay lines, the disadvantages of which are large dimensions and the complexity of changing the delay time. The interface components under consideration are intended for use in test diagnostics devices that have a multiprocessor structure, which increases the speed of forming test actions and reference reactions. The performed functional modeling and debugging of strobe signal generators confirmed the feasibility of the designs. The proposed interface of the test diagnostics device allows performing test diagnostics of modern high-speed chips and semiconductor memory modules at the operating frequency, which increases the reliability of the results obtained. Interface components can be used by manufacturers of test diagnostics tools for modern high-speed storage devices.

Row hammer avoidance analysis of DDR3 SDRAM

A DDR3 SDRAM test setup implemented on the Griffin III test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests for different manufacturing technologies. The row hammer effect is depending on the number of stress activation cycles. The analysis is extended to an avoidance scheme with refreshes similar to the Target Row Refresh scheme for the DDR4 SDRAM technology.

The digital controller for power supplies in HIAF

High Intensity Heavy Ion Accelerator Facility (HIAF) project has been proposed by Institute of Modern Physics, Chinese Academy of Sciences (IMP) for high power heavy ion researches. Due to the unique requirements of the Booster Ring (Bring) in HIAF, a digital controller is used as the controlling system of power supplies to achieve high performances. This paper explains the hardware and software architecture of the digital controller. It uses Cyclone V SX SoC FPGA which integrates dual-core ARM Cortex-A9 MP Core processor. The controller consists of high precision ADC, DAC, optical fibre modules, DDR3 SDRAM and Gigabit Ethernet modules. The PI regulation and PWM modulation have been realized in FPGA. The data pre-setting, web service, database, power supplies detection and protection management have been established in ARM. Finally, the results of prototype output measurements prove that this design is feasible and qualified.

A 1.1-V 10-nm Class 6.4-Gb/s/Pin 16-Gb DDR5 SDRAM With a Phase Rotator-ILO DLL, High-Speed SerDes, and DFE/FFE Equalization Scheme for Rx/Tx

A 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 is presented in 10-nm class CMOS technology. Various functions and circuits' techniques are newly adopted to improve performance and power consumption compared with DDR4 SDRAM. First, to realize two times higher speed than DDR4, the injection-locked oscillator (ILO) delay locked loop (DLL) is adopted for the low jitter high-speed performance. The proposed DLL with phase rotator (PR) and ILO allows to minimize the clock tree of DRAM, lowering skew and jitter in the DRAM internal clock path. Second, for the high-speed write operation, DQS gate opening control and write leveling are very important to minimize the turnaround time of DRAM, and thus new sequence and logic for the write-level training are introduced in this article. Third, to maximize the data valid window of read DQs, duty cycle adjustable serialize circuit methods are proposed. Finally, to improve the interface speed, the decision feedback equalization (DFE) and feedforward equalization (FFE) are adopted to Rx and Tx, respectively. By implementing all the items mentioned earlier, the 1.1-V 6.4-Gb/s/pin 16-Gbit DDR5 achieved 6.4-Gb/s/pin performance at 1.05-V V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">DD</sub> , with its power bandwidth efficiency 30% higher than that of DDR4.

Design of Real Time Video Image Acquisition and Processing System Based on FPGA

Based on characteristics of instantaneously, large capacity and miniaturization of digital image acquisition and processing technology, a real-time video image acquisition and processing circuit system was designed, FPGA was used as the center of controlling the whole system and the center of processing image data. With DDR2 SDRAM the core component of high speed storage module, and CMOS 7670 the video image acquisition device. Through the Quratus II and Modelsim software for edge detection algorithm mand the control process, each module of the hardware design and simulation, the realization of the video images from the collection and storage to the treating and display, which shows smooth, clear and real-time.

Unsupervised image thresholding: hardware architecture and its usage for FPGA-SoC platform

ABSTRACTOtsu’s global automatic image thresholding operation is used in various image processing applications. It needs computation of normalized cumulative histogram, mean and cumulative moments that are compute-intensive operations. In this paper, a custom architecture is presented for an efficient computation of Otsu’s algorithm along with its utilization as an intellectual property (IP) core in a field programmable gate array (FPGA) based system-on-chip (SoC) environment for the application of connected component analysis (CCA). A self-normalization technique is employed, where single-cycle, read–modify–write operations are performed with block random access memories (BRAMs) and digital signal processing (DSP)slices. The architecture is designed for 640 × 480 size of images that are captured by a high-resolution analouge camera and buffered in a DDR2 SDRAM of Xilinx ML-507 platform at 25.175 MHz clock frequency. The embedded PowerPC processor core is used to control the frame acquisition process. Experimental results on Virtex-5 xc5vfx70t FPGA device show that the architecture utilizes 1.4% slices, 2.7% BRAMs and 3.9% DSP48E slices. The total power consumption of the design is 1440.59 mW. The proposed architecture as an IP core is able to work in real-time with standard VGA resolution video and requires low computational resources.

Design and Implementation of a DDR2 SDRAM Controller for Audio Data on a Reconfigurable Platform

Design and Implementation of a DDR2 SDRAM Controller for Audio Data on a Reconfigurable Platform

Failure signature analysis of power-opens in DDR3 SDRAMs

Open defects in power pins can only be diagnosed indirectly, and these diagnoses are a challenging task in failure analysis due to the failure signature's aliasing to other issues. Open defects cannot be detected by traditional DC-type test methods and can remain a potential risk in stressful device operation. In this work, error signatures in power open faults are experimentally probed to better understand electrical signatures induced by power-open. The power open faults are intentionally injected into a DDR3 SDRAM test platform. The power network inside the DDR3 SDRAM is experimentally found to be asymmetrical. Power-open defects in one power pin produce a range of power noise (0–65 mV), depending on the location of the power pin.

Easy Signal Generation to DDR2 with Low Access Time

Generating signals for DDR2 SDRAM is a complex process and requires large hardware to do so. A Memory Interface Generator is provided by Xilinx IP, but generating the signals for MIG is also complex. In this paper, a design has been proposed that writes and reads to DDR2 SDRAM in bursts which saves time. A read operation is also done after one read operation requested by the user when if the device is idle. This operation of writing and reading in bursts and read operation when the device is idle saves access times. This design reduces the access time from 135ns to 35.826ns approximately.

Study of proton radiation effect to row hammer fault in DDR4 SDRAMs

This paper shares the effects of row hammer fault through high-energy proton radiation. The significance of row hammer fault is highlighted in terms of two different technologies in DDR4 SDRAM.Row hammer stress prevents nearby storage cells from maintaining storage data within the retention time of 64-ms. The stress is worsened by the radiation damage in silicon due to the high-energy particles.Proton-based radiation damage tests were performed with DDR4 SDRAM components from two different technologies. Experiment results showed that after proton irradiation, the number of bit errors caused by the row hammering test increased about 41% and 66% in technologies 2x-nm and 2y-nm, respectively. With 2y-nm technology, bit errors started to appear from 5K Number of Hammering (NHMR)—the equivalent of 500-μs retention time. For 2y-nm components, more than 90% of failed words had multiple failed cells, which could not be corrected by Single Error Correction and Double Error Detection (SEC-DED) codes.

Bank-Group Level Parallelism

DDR4 SDRAM introduced a new hierarchy in DRAM organization: bank-group (BG). The main purpose of BG is to increase I/O bandwidth without growing DRAM-internal bus-width. We, however, found that other benefits can be derived from the new hierarchy. To achieve the benefits, we propose a new DRAM architecture using the BG-hierarchy, leading to a creation of BG-Level Parallelism (BGLP). By exploiting BGLP, the overall parallelism grows in DRAM operations. We also argue that BGLP is a feasible solution in the cost-sensitive DRAM industry because the additional cost is negligible and only cost-insensitive area needs to be modified.

A row hammer pattern analysis of DDR2 SDRAM

A DDR2 SDRAM test setup implemented on the Griffin III ATE test system from HILEVEL Technologies is used to analyse the row hammer bug. Row hammer pattern experiments are compared to standard retention tests. The analysis confirms that the row hammer effect is caused by a charge excitation process depending on the number of stress activation cycles. The stress has to occur in the local neighborhood of the cells under test. Shallow impurity levels support the responsible charge carrier transport process in the used DDR2 SDRAM technology.