DC Parameters Research Articles

Response of Soil Detachment Capacity to Hydrodynamic Characteristics Under Different Slope Gradients

The mechanism of soil detachment on steep slopes is obviously different from that on gentle slopes. However, the slope effect of soil detachment remains unclear. The objective of this study was to quantify the slope effect of soil detachment capacity at the varying hydrodynamic characteristics. In this study, the soil detachment capacity (Dc) on clay loam and hydrodynamic characteristics were measured by conducting the runoff scouring experiments at 10 slope gradients (1.7–57.7%) and 5 unit flow discharges (0.022–0.089 m2·min−1). The results showed that the relationships between Dc and hydrodynamic parameters were affected by slope gradient. Based on the optimal functional relationship, the hydrodynamic characteristics (flow velocity, flow shear stress, stream power, unit stream power, and unit energy) calculated by maximum and minimum Dc in this study changed by 19.91–95138.10%, and the Dc calculated by the maximum and minimum hydrodynamic characteristics could differ by up to nine orders of magnitude. Overall, the power function of hydrodynamic parameters was superior to the linear function in different slope gradients. The stream power was the best predictor for Dc compared with other hydrodynamic parameters. For all combinations of slope gradients, the adjusted coefficient of determination (Adj. R2) of the power relationship between Dc and stream power was 9.41–27.40% higher than it was between Dc and other hydrodynamic parameters. The coefficient and index of power function for different hydrodynamic parameters showed a trend change with increasing slope gradient, indicating that there was a slope effect on Dc. Further analysis found that Dc could be well predicted using a power combination equation of slope gradient, flow velocity, and flow depth (Adj. R2 = 0.96). This study helps to better understand the mechanism of soil detachment and emphasizes that the slope effect should be considered when establishing a soil detachment equation.

Device Reliability of Negative Capacitance Source Pocket Double Gate TFETs: A Study on Temperature and Noise Effects

This study investigates the reliability of a negative capacitance source pocket double gate tunnel field-effect transistor (NC-SP-DGTFET) by examining the effects of temperature and various noise components on its performance. The research focuses on key DC parameters, including the transfer characteristics, subthreshold swing, and the ION/IOFF ratio, evaluated across a temperature range from 250 to 450 K. Additionally, the study explores the radio-frequency performance of the device by assessing how temperature impacts transconductance (gm), cut-off frequency (fT), gate capacitance (Cgg), intrinsic delay, and the transconductance frequency product. Noise performance metrics are also analyzed, focusing on the drain current noise power spectral density (SID) and gate voltage noise power spectral density (SVG). The study considers the contributions of diffusion, generation-recombination (G-R), and flicker noise components and at 300 K, SID and SVG showed peak values of 5.08 × 10−26 A2/Hz and 2.67 × 10−16 V2/Hz, 5.73 × 10−18 A2/Hz and 3.22 × 10−10 V2/Hz, and 1.33 × 10−25 A2/Hz and 1.19 × 10−14 V2/Hz, respectively. The analysis reveals that flicker noise is predominant at lower frequencies, while diffusion noise becomes more significant at higher frequencies. However, G-R noise is the most dominant across all frequencies examined. These findings provide crucial insights for optimizing the design and performance of NC-SP-DGTFETs in low-power applications.

Device and circuit-level performance evaluation of DG-GNR-DMG vertical tunnel FET

This work presents the comparative study of Graphene Nanoribbon (GNR) based channel Double Gate (DG) Dual Gate Material (DMG) Vertical tunnel Field Effect Transistor (VTFET) performance with all Silicon material Tunnel Field Effect Transistor. The two-dimensional (2D) material GNR has been proposed in the channel material to enhance the device performance due to its low bandgap, high mobility, and high saturation velocity. The proposed device's DC, RF, and circuit-level performance analysis has been carried out for the first time. GNR-based channel VTFET shows a better average subthreshold swing (SSAVG) of 16 mV/decade compared to Silicon Vertical Tunnel FET (36 mV/decade) at a drain voltage VDS = 0.5 V. The study of temperature effects on the DC parameters is also included along with the analog/RF FOMs for the proposed two structures. In addition, the performances are compared with other reported works; it is observed that DG-GNR-DMG-VTFET offers better results than Silicon (Si)-based VTFET and other said TFET work. Finally, circuit-level analysis has been done by designing inverter and ring oscillator circuits for the proposed structures, and performance is compared in these two devices. The market-available Silvaco ATLAS TCAD simulator has been used for device-level simulation. Further, circuit-level analysis has been carried out in the Cadence Virtuoso tool using a look-up table-based Verilog-A model.

Analog and linearity performance analysis of ferroelectric vertical tunnel field effect transistor with and without source pocket

AbstractThis study examines the electrical performance characteristics of a ferroelectric vertical tunnel field‐effect transistor (TFET) with and without a source pocket (Si0.5Ge0.5). The incorporation of Germanium in the source of the TFET aims to enhance the on‐current. The Silvaco TCAD simulation tool is utilized to simulate the proposed structure. To improve device performance, a ferroelectric layer with a vertical length is employed in the gate of the TFET. When the ferroelectric layer partially controls the channel region, device characteristics, such as on‐current and subthreshold swing (SS) can be improved (i.e., ION = 15.21 × 10−5 A/μm, ION/IOFF = 5.03 × 109, and a minimum SS of 20.87 mV/decade at 300 K). This article studied a comparison between ferroelectric vertical TFETs and nonferroelectric vertical TFETs, as well as ferroelectric vertical TFETs with and without source pockets. The comparison is done on the basis of DC and RF parameters. Analysis of this comparison represents that ferroelectric vertical TFET with source pocket has improved characteristics.

GaSb/Si Heterojunction Based Pocket Engineered Vertical Non-Uniform Channel Double Gate TFETs for Low Power Applications

This article compares the performance of two Vertical Non-Uniform Channel Double Gate Tunnel Field Effect Transistors (VNUCDGTFETs), a normal all-Silicon Tunnel Field-Effect Transistor (TFET) having a pocket and another one a Gallium Antimonide/Silicon heterojunction TFET with pocket. GaSb is a III-V narrow energy band gap material, employed in the source area of the TFET structure to decrease the tunneling width and thus to make more number of carriers capable enough to tunnel through the heterojunction. The proposed source pocket heterojunction non uniform channel TFET presents superior performance as compared to the conventional non uniform channel vertical TFET with a pocket, regarding a larger ION/IOFF ratio, a reduced sub-threshold swing, and a smaller threshold voltage at VDS = 0.5 V. Furthermore, the proposed TFET device undergoes a comprehensive analysis of both DC parameters and various analog/RF parameters.

Unveiling the influence of temperature and interface traps on the performance of source-all-around vertical TFET

This study investigates the electrical performance of a line-tunneling based source-all-around vertical Tunnel Field-Effect Transistor (SAA-VTFET) under diverse temperature and trap charge conditions. The proposed device achieves remarkable performance improvements across DC and AC parameters by employing strategically engineered III-V semiconductors and a wide source-channel tunneling heterojunction. Key metrics like on-state current (ION = 6.35 × 10−5 A/μm), off-state current (IOFF = 3.17 × 10−17 A/μm), threshold voltage (VT = ⁓0.18V), subthreshold swing (SSavg = ⁓7 mV/dec), transconductance (gm = 0.16 mS), cut-off frequency (fc = ⁓0.42 THz), gain bandwidth product (GBP), delay (τ), and various capacitances are thoroughly analyzed. Sentaurus TCAD 3D simulations employed in this study demonstrate the promising future of SAA-VTFETs in low-power and high-speed electronics.

A machine learning approach for optimizing and accurate prediction of performance parameters for stacked nanosheet transistor

In this article, the possibilities of accurate prediction of wide range of parameters and optimizing the same through machine learning (ML) approach have been demonstrated for the multi stacked nanosheet transistor (NSFET). The machine is trained by the generated data of the tedious calibrated technology computer aided (TCAD) simulations. An innovative strategy is employed that combines ML with device simulations. Numerous devices are simulated with different geometric parameters like height, width, length and equivalent oxide thickness of the channel. The input, output, and CV characteristics are extrapolated from the simulation which is predicted by ML models. The DC, Analog and RF parameters are derived with a domain expertise approach. The device parameters are anticipated with actual values by the ML approach. Random forest regression, linear regression, polynomial regression and decision tree regression are employed for the prediction of the performance parameters. Random forest regression models provide significant R2 score with minimal error percentage. It indicates that TCAD-augmented ML can be considered an alternative to device simulation due to its reduction in computational cost. This work can also be treated as a benchmark for accurate prediction of the NSFET.

Design and simulation of a germanium source dual‐metal dopingless tunnel FET as a label‐free biosensor

AbstractThis study presents a new dual‐metal dopingless tunnel field effect transistor with a Germanium source (GeS‐DM‐DLT) for label‐free biomolecule detection. Introducing a Ge source and dual‐metal gate provides improved drain current. We have considered an L‐shaped cavity at the top and bottom source metal region for investigating the sensitivity. The biosensor's sensitivity has been measured using the neutral biomolecules' dielectric constants (varying the k‐values in the cavity). The sensor's DC performance is investigated using transfer characteristics, BTBT rate, energy band, and electric field variation for different k‐values. The sensitivity performance of the proposed biosensor is evaluated in terms of different DC parameters (drain current, surface potential, subthreshold swing, interband tunneling rate, electric field) and RF parameters (parasitic capacitance, transconductance, cut‐off frequency, maximum frequency). The suggested biosensor offers a much‐improved SON of 9.86 × 108 and SRATIO of 1.94 × 104 for a dielectric constant of 22.0 at room temperature. Further research has been done to study the effects of dielectric materials, interface trap carriers (ITC), and temperature on drain current, drain current sensitivity, and other sensitivity parameters. The article also includes investigating the influence of the fill factor on sensitivity performance. The GeS‐DM‐DLT sensor performs best in fully‐filled conditions compared to the partially‐filled condition inside the cavity region.

DFT based atomic modeling and temperature analysis on the RF and VTC curve of high-k dielectric layer-assisted NCFET

In this report, Density Functional Theory (DFT) based calculation using a Quantum Atomistic Tool Kit (ATK) simulator is done for the hafnia-based ferroelectric material. The band structure, projected density of states (PDOS), and Hartree potential (VH) are taken into account for hafnium oxide (HfO2) and silicon-doped hafnium oxide (Si-doped HfO2). Further, we analyze the temperature variation impact on analog parameters and voltage transfer characteristic (VTC) curve of inverter application of Modified Negative Capacitance Field-Effect-Transistor (NCFET) using the Visual Technology-Computer-Aided-Design (TCAD) simulator. The Modified NCFET structure enhances the DC parameters like leakage current (IOFF) and Subthreshold Swing (SS) compared to the conventional NCFET structure. With the temperature impact, the variation in the parameters of Modified NCFET is discussed at 250 K, 275 K, 300 K, 325 K, and 350 K like transconductance (gm), output conductance (gd), early voltage (VEA) shows the increment as we move from 250 K to 350 K. The short channel effects (SCEs) like Drain Induced Barrier Lowering (DIBL) and Subthreshold Swing (SS) decrease with the temperature fall at 32.98% and 34.74%, respectively. Further, the VTC curve, Noise Margin (NM), and propagation delay of Modified NCFET-based inverter are discussed with the impact of temperature. The propagation delay for the circuit decreased by 67.94% with the rise in the temperature. These factors show that the Modified NCFET-based inverter gives a fast switching performance at high temperatures.

Biogas Reforming Combined with Co-Electrolysis inside AC:DC Operated Solid Oxide Electrolyser Cells

Upgrading biogas into added-value fuels and chemicals is seen as one of the main pathways to reduce carbon dioxide emissions from the energy sector. In particular, green methanol represents a strategical product due to its high versatility in the transportation and chemical industry. Biogas reforming is a key step in the upgrading process and it can be integrated with Power-to-X technology. The reforming can be conducted using Solid Oxide Electrolysers (SOEs). Furthermore, the outlet syngas composition can be adjusted and optimized for methanol production, via the additional production of hydrogen provided by the simultaneous steam electrolysis.This research focuses on analysing the effects of Dynelectro’s patented AC:DC operation [EP3719171A1, WO2020/201485A1, EP3947779A1] applied to biogas-fed SOE cells. The principle of this novel operating condition is to impose an alternating current over a direct current, which for SOE translates into reversing the polarization of the cell and having a regular switch between fuel cell mode and electrolysis mode. When performing steam electrolysis, the benefits of AC:DC operation are already proven to consist in reduced degradation, due to impurities removal, and enhanced temperature control during dynamic operations [Skafte, 2022]. When the SOE cell is fed with a composition of methane, carbon dioxide and steam, the main issue to solve is the high energy requirement from the steam reforming process and the steam electrolysis performed simultaneously. In fact, both reactions are endothermic at SOE operating conditions (750°C and ambient pressure), with an enthalpy difference of respectively 225 kJ/mol and 248 kJ/mol. In this regard, the AC:DC operation can provide additional heat, because of the polarization switch to fuel cell mode, and avoid the temperature drop within the SOE. Moreover, it is possible to tune the rate of co-electrolysis and biogas reforming.A mathematical model is developed to simulate biogas reforming in an AC:DC operated SOE cell. The model includes mass transport, electrochemistry, catalytic reactions and energy balance. The composition of biogas is assumed to be mainly methane and carbon dioxide. By operating both in DC and AC:DC, this gives a first indication of the extent of the expected benefits. To validate the model, laboratory experiments are performed, where single SOE cells are operated in an imitated biogas compositions and the outlet gas is analysed using gas chromatography. These experiments include current-voltage (i-V) curves and electronic impedance spectroscopy (EIS) analysis, which can be used to measure the performances of such operations by observing the cell voltage and the degradation rate.The results from ordinary direct current operation and Dynelectro’s AC:DC operation are compared in terms of syngas composition and operating voltage. The optimal composition of syngas for methanol synthesis, consisting of a ratio of hydrogen to carbon monoxide of approximately 2 and low traces of methane, is achieved. Reduced methane content in the outlet gas is shown when operating the SOE cells with AC:DC current, compared to DC operations. The latter shows a CH4 molar fraction of approximately 1%, while the former allows the CH4 concentration to go below this level, depending on the AC:DC parameters. It is found that the rate of methane and carbon dioxide conversion is dependent on the frequency and duty cycle of the AC:DC operation. The achievement of stable conditions during these operations leads to an optimized biogas to syngas conversion, and a simplified overall biogas to methanol process.

(Invited) In-Depth Understanding of the Key Contributors to the Total Flicker Noise in Advanced Logic Devices

The aim of this work is to perform an in-depth analysis in order to identify the key contributors to the total flicker noise in advanced MOSFET technologies, e.g. UTBOX, FinFET or Gate-all-around (GAA) nanowire or nanosheet FET devices.In this abstract, as an example, we will focus on p-type gate all around silicon vertical nanowire devices fabricated at imec. The transistors have a fixed gate length (LG) of 50 nm and 1200 nanowires in parallel (N), each nanowire (NW) having a diameter (WNW) of 20 nm. The total width (W) of the device is calculated as . The gate stack corresponds to an equivalent oxide thickness (EOT) of 0.9 nm. A full description of the process flow of the devices is presented in [1]. Comparison between the Y-function strategy of [2] and McLarty methodology [3] permits to estimate with accuracy the DC parameters necessary for low frequency noise modelling, which are summarized in Table 1.Typical low frequency noise spectra are shown in Figure 1. The methodology for the estimation of the low frequency noise parameters is described in [4], but it is obvious that the noise spectra are dominated by 1/f noise and only few Lorentzian contributions appear for some gate voltage polarization. As the corresponding flicker noise levels (K f ), plotted in Figure 2 present a plateau and rise with the increase of the applied gate voltage, the responsible 1/f noise mechanism should be related to the carrier number or correlated carrier number fluctuations mechanism, with a possible contribution of the access resistance 1/f noise.Firstly, the model described in [5-9] expressed as in equation (1) is employed. A linear dependence of the square root of the 1/f noise levels on the measured Id/gm is observed in Figure 3, permitting to estimate from the intercept and slope the flat-band noise level (Svfb) and the W coefficient, respectively. Using the methodology of [9] the estimated W parameter is corrected by the access resistance influence. Good agreement with experimental data in strong inversion may be observed in both cases (Figure 4).Secondly, the model which considers the small signal model of the MOSFET is used, assuming that the channel resistance noise and access resistances noise are uncorrelated noise sources [2,10,11]. The model may be expressed by equation (2) ((13) of [11]), in order to make no assumption concerning the gm/gch ratio. Beyond the threshold voltage, the impact of the cannot be neglected, as observed from Figure 5. It may be observed from Figure 6 that the correlated number fluctuation and mobility noise mechanism cannot explain the flicker noise behavior in very strong inversion, and an additional contribution of the access resistances noise may be considered in order to agree with the experimental data.The noise parameters estimated to agree with the experimental data for both models are summarized in Table 2. It is interesting to note that the experimental data may be explained by both models, but the key contributors are not the same: only correlated number fluctuations and mobility noise mechanism for the first model, and correlated number fluctuations and mobility and access resistance noise mechanisms contribution for the second one. Moreover, the estimated flat-band noise levels are not the same, a much lower Svfb is obtained when the first model is employed. Considering the access resistance impact may correct the W coefficient, but leads to even lower flat-band noise levels, as already reported in [9].These results lead to some questioning about which of these two models is most accurate and give good indications on the key contributors and estimated parameters of the total flicker noise.

Electrical performance estimation and comparative study of heterojunction strained and conventional gate all around nanosheet field effect transistors

Abstract In this paper, we propose a novel type of Gate All Around Nanosheet Field Effect Transistor (GAA NS FET) that incorporates source heterojunctions and strained channels and substrate. We compare its electrical characteristics with those of the Heterojunction Gate All Around Nanosheet Field Effect Transistor (Heterojunction GAA NS FET) and the Conventional Gate All Around Nanosheet Field Effect Transistor (Conventional GAA NS FET). We investigate the impact of electrostatic control on both DC and analog parameters such as gate capacitance (C gg), transconductance g m, and cut-off frequency (f T) for all three device types. In our Proposed GAA NS FET, we employ Germanium for the source and substrate regions, Silicon/Germanium/Silicon (Si/Ge/Si) for the channel, and Silicon for the drain region. The introduction of strain into the nanosheet and the use of a heterojunction structure significantly enhance device performance. Before utilizing a model to analyze a semiconductor device, it is crucial to accurately determine and elaborate on the model parameters. In this case, we solve the Density Gradient (DG) equation self-consistently to obtain the electrostatic potential for a given electron Fermi-level distribution, use the Shockley-Read-Hall (SRH) equation to estimate carrier generation, account for bandgap narrowing in transport behavior, and consider auger recombination. Our general results indicate a notable improvement in drain current, transconductance, and unity-gain frequency by approximately 42%, 53%, and 31%, respectively. This enhancement results in superior RF performance for the Proposed GAA NS FET compared to both the heterojunction GAA NS FET and the conventional GAA NS FET.

Effect of lattice heating on the switching performance of a silicon‐gate all around dielectric window spaced‐multi‐channel MOSFET

AbstractIn this article, analysis of heating effect for a range of thermal resistance () and different ambient temperatures on the DC parameters of the proposed Silicon‐Gate All Around Dielectric Window Spaced‐Multi‐channel (Si‐GAA‐DWS‐multi‐channel) MOSFET is carried out. The performance of the device is examined through 3D‐ATLAS TCAD simulator, by performing the numerical and electrothermal analysis. Due to cylindrical dimension, the nanowire FETs undergoes undesirable self/lattice‐heating. The lattice heating of the device is calculated with respect to various device parameters such as channel length, drain‐source voltage, thermal resistance, ambient temperature, on‐current , and off‐current . The proposed device parameter has been compared with the existing devices, mainly with Silicon‐Nanowire‐Dielectric Pocket Packed MOSFET (Si‐NW‐DPP FET) and Silicon‐Nanowire MOSFET (Si‐NW FET). The Si‐GAA‐DWS‐multi‐channel FET is found to be as the better device than the other two structures, as the leakage current of the device is improved by 1 and 2 decades, drain current increases by 1 and 1 decade, a minimum SS of 63.271 mV/dec and a minimum DIBL of 26.172 mV/V, respectively. The lesser the SS, the faster will be the device; hence the proposed structure can be considered as the finest prospect for VLSI/ULSI electronic chips.

Modified Allen Test Assessment via Imaging Photoplethysmography

Abstract The modified Allen test (MAT) is a widely used tool to examine the perfusion capacities of the arteries (ulnar or radial) of the hand. In clinical practice, MAT is utilized to ensure that in the event of occlusion, remaining vessels guarantee sufficient hand perfusion. This work shows that perfusion assessment via imaging photoplethysmography (iPPG) can be used to assess MAT. We captured the hands of seven subjects with a standard RGB camera while performing a MAT. Out of these captured video recordings, the iPPG signal was extracted via plane-orthogonal-to-skin transformation. Based on these extracted signals, we derive the heart rate, signal-to-noise ratio, DC parameter, and correlation with a reference iPPG signal to determine if an Allen test was pathological or inconspicuous. For all seven subjects, the results of our MAT assessment were identical to the medical expert’s assessment. This paper presents a procedure and initial thresholds for objectively evaluating and quantifying MAT.We show how globally and locally calculated parameters can be used to assess the perfusion of the investigated hand. This analysis makes it possible to quantify the exact point in time when the perfusion is again sufficient. If a reperfusion problem occurs, we are able to localize the spatial regions of occurrence. The presented hardware setup is affordable and can be easily installed and used in every doctor’s office.

Optimizing U-Shape FinFETs for Sub-5nm Technology: Performance Analysis and Device-to-Circuit Evaluation in Digital and Analog/Radio Frequency Applications

FinFET is considered as the potential contender in the era of Multigate FETs. This manuscript for the first time presents the structural variations for Junctionless FinFET devices at IRDS sub-5nm technology node. Four JL-FinFET novel structures are proposed here namely Junctionless Middlegate-U shape FinFET (JL-MG-U-FinFET), Junctionless U shaped FinFET (JL-U-FinFET), Junctionless Inverted-U shaped FinFET (JL-Inv-U-FinFET), and Junctionless Double gate- Inverted-U shaped FinFET (JL-DG-Inv-U-FinFET). The electrical and analog/RF performances of these structures are compared and it is found that JL-DG-Inv-U-FinFET gives better performance in terms of minimizing short channel effects as well as in terms of analog/RF characteristics. The ION/IOFF ratio values for (JL-MG-U-FinFET, JL-U-FinFET, JL-Inv-U-FinFET, and JL-DG-Inv-U-FinFET) are observed as 8.5 × 106, 1.2 × 109, 2.04 × 108, and 1.1 × 1010, respectively. Similarly, the SS values are noted as 93.44 mV dec−1, 70.87 mV dec−1, 70.61 mV dec−1, and 62.1 mV dec−1 for the respective configurations. Furthermore, the effect of variation in geometrical parameters such as gate length (Lg), U-shaped fin width (WU-fin), and U-shaped fin height (HU-fin) on DC and analog/RF characteristics is also explored. It has been observed that the DC parameters such as Ion/Ioff ratio, SS are better for higher Lg, lower WU-fin, and higher HU-fin. Moreover, the JL-DG-Inv-U-FinFET based Common Source (CS) amplifier produced a gain of 5.2. The results reported in this study will aid device engineers in selecting better geometrical parameters to achieve improved JL-DG-Inv-U-FinFET performance.

GaSb/GaAs Type‐II heterojunction GAA‐TFET with core source for enhanced analog/RF performance and reliability

AbstractFor the first time, a novel source extension heterojunction gate‐all‐around tunnel FET (SE‐GAA‐TFET) is proposed and examined using Synopsys TCAD simulator in this manuscript. SE‐GAA‐TFET is found to exhibit improved performance in terms of various analog/RF and DC parameters. As channel/source (C/S) interface and electric field exerted by gate are perpendicular to each other, radius of channel is downscaled to enhance electric filed, without reducing area of the tunneling. Furthermore, the presence of GaSb/GaAs heterojunction at C/S interface leads to reduction in the effective band overlap, which helps a great number of mobile charges to tunnel through C/S boundary at ON‐state. The consequences of variation in different geometrical metrics are evaluated to optimize the device performance. SE‐GAA‐TFET is found to offer a current switching ratio (CSR) of ~1013 along with 32.2 mV dec−1 of average sub‐threshold swing (SSAVG). Furthermore, improvement in transconductance and parasitic capacitance boost the cut‐off frequency of SE‐GAA‐TFET up to 37 GHz. Next, both positive and negative traps are introduced at S/C interface and the study reveals that there is no much deviation in parameters of the transfer characteristics like ION, SSAVG, and IOFF of SE‐GAA‐TFET. Next, proper benchmarking is done to compare the performance of the SE‐GAA‐TFET with similar devices available in literature and it is found that proposed SE‐GAA‐TFET exhibits better DC performance due to improved electrostatic behavior. Finally, SE‐GAA‐TFET is found to offer better fall time along with full‐voltage swing when deployed in a resistive load inverter.

New optimized HIT solar cell using wide-bandgap nc-3C-SiC:H as a window layer

This study focuses on the investigation of HIT solar cell using nanocrystalline hydrogenated cubic silicon carbide (nc-3C-SiC:H) as a window layer. The selection of nc-3C-SiC:H is motivated by its wide bandgap, high electron drift velocity, and exceptional optical, electrical, and structural properties. Employing SCAPS-1D simulator, a comprehensive simulation analysis of thin nc-3C-SiC:H-based solar cell was conducted. By analyzing the current–voltage and quantum efficiency curves, the impact of doping concentration in the window layer was examined, covering a range from [Formula: see text] to [Formula: see text]. A rapid degradation of [Formula: see text] was observed for high doping concentrations. Additionally, the temperature dependence of external DC parameters for the temperatures 273, 300, and 318[Formula: see text]K was explored under AM1.5G and AM1.5D sunlight spectra. The application of two distinct light spectra resulted in the DC parameters exhibiting minimal variation or similarity. The study also took into account the influence of window thickness variation, temperature, and doping concentration. The findings demonstrate a remarkable influence of temperature and doping concentration on the DC parameters. [Formula: see text] value of 30.29[Formula: see text]mA/cm2 was achieved with a 3-nm thickness and an optimal efficiency of 19.48% was registered with a doping concentration of up to [Formula: see text], showcasing the promising potential of nc-3C-SiC:H.

Charge-plasma-based inverted T-shaped source-metal dual-line tunneling FET with improved performance at 0.5 V operation

In this paper, a charge plasma-based inverted T-shaped source-metal dual line-tunneling field-effect transistor (CP-ITSM-DLTFET) has been proposed to improve the ON current (ION) by increasing the line-tunneling area. In the proposed structure, the charge plasma technique is used to induce the dopants in the source and drain regions. Due to its doping-less structure, the proposed CP-ITSM-DLTFET is immune to random dopant fluctuations and does not require an expensive thermal annealing technique. This makes the proposed device’s fabrication easier and more efficient. The proposed CP-ITSM-DLTFET comprises an inverted T-shaped source metal (sandwiched between the Si-channel) and creates gate-to-source overlap and increases the tunneling area vertically on both sides of the Si-channel. The vertical line-tunneling area in the proposed structure makes the device able to be aggressively scaled compared to conventional TFETs for future technology. The proposed CP-ITSM-DLTFET outperforms almost all pre-existing dopingless TFETs in terms of DC and RF parameters. The switching performance (like high ION = 31.88 uA um−1, steeper AVSS = 23.42 mV dec−1 (over 12-order of drain current), and high ION/IOFF ratio of 1.6 × 1013) and the RF performance (like transconductance (gm) = 0.37 mS, Cut-off frequency (fT) = 90.18 GHz, and Gain Bandwidth product (GBW) = 32.3 GHz) of the proposed CP-ITSM-DLTFET are superior to almost all pre-existing Si, SiGe, and Ge based doping-less TFETs. Moreover, the proposed CP-ITSM-DLTFET-based CMOS inverter has also been comprehensively studied in the paper, showing a good noise margin NMH = 0.198 V (39.8% of VDD) and NML = 0.206 V (41.2% of VDD) with a high voltage gain of 30.25 at VDD = 0.5 V, suggesting great potential for future low power applications.

Novel Y-function based strategy for parameter extraction in S/D asymmetric architecture devices and low frequency noise characterization in GAA Si VNW pMOSFETs

In this work, DC and low frequency noise measurements are performed in p-channel gate-all-around (GAA) silicon vertical nanowire (Si VNW) MOSFETs. The DC measurements highlight asymmetry in the drain current and transconductance transfer characteristic even in linear operation, at an applied drain voltage of −50 mV. A novel Y-function based strategy for parameter extraction in S/D asymmetric devices is proposed. This novel strategy allows the estimation of the value of each access resistance, from source and from drain sides, respectively, and allows overcoming the device asymmetry to provide an accurate extraction of the main DC parameters. The low-frequency noise studies on forward and reverse operation mode, demonstrate that the 1/f noise in both modes can be explained by the correlated carrier number (Δn) and mobility fluctuation (Δμ) mechanisms, with additional contribution of the access resistance noise in strong inversion.

Buried interfacial gate oxide for tri-gate negative-capacitance fin field-effect transistors: approach and investigation

Negative-capacitance fin field-effect transistors (NC-FinFETs), due to their superior gate electrostatics and dominance over short channel effects (SCEs), have been a key technology among conventional devices. The improved device performance in terms of the various engineering practices has paved the way for the advancement of NC-FinFETs. In the following work, we have proposed a novel buried oxide strategy for the NC-FinFET architecture, in which we have altered the depth of the interfacial gate oxide (IGO) layer inside the channel and analyzed the performance characteristics using TCAD Sentaurus. First, we varied the IGO thickness that was buried inside the channel and performed a comparative analysis between the DC, mixed-mode, and SCE parameters for the various buried configurations of the proposed NC-FinFET in order to realize the optimized depth. We also present the tolerable degradation in the circuit characteristics that occurs with the varying buried IGO (BIGO) depth. It can be inferred from the presented interface trap discussion that the idea of BIGO thickness holds well for low-power electronics.