Unveiling the influence of temperature and interface traps on the performance of source-all-around vertical TFET

Abstract

This study investigates the electrical performance of a line-tunneling based source-all-around vertical Tunnel Field-Effect Transistor (SAA-VTFET) under diverse temperature and trap charge conditions. The proposed device achieves remarkable performance improvements across DC and AC parameters by employing strategically engineered III-V semiconductors and a wide source-channel tunneling heterojunction. Key metrics like on-state current (ION = 6.35 × 10−5 A/μm), off-state current (IOFF = 3.17 × 10−17 A/μm), threshold voltage (VT = ⁓0.18V), subthreshold swing (SSavg = ⁓7 mV/dec), transconductance (gm = 0.16 mS), cut-off frequency (fc = ⁓0.42 THz), gain bandwidth product (GBP), delay (τ), and various capacitances are thoroughly analyzed. Sentaurus TCAD 3D simulations employed in this study demonstrate the promising future of SAA-VTFETs in low-power and high-speed electronics.