DC Operating Research Articles

DC operating points of Mott neuristor circuits

In 1960 Hewitt Crane conceptualized neuristors as electronic logic networks that could mimic action potential generation by biological neurons. In 2012 Mott memristors were presented as nano-scale electronic devices for physically constructing neuristor networks. Both the original Mott memristor model and the simplified model presented in 2020 are stiff nonlinear first-order ordinary differential equations (ODEs) that describe the voltage controlled threshold switching and current controlled negative differential resistance, attributed to a Mott insulator-to-metal phase transition. By design, a Mott neuristor contains two identical Mott memristors plus linear resistors and capacitors (no inductors), which enables alternating threshold switching by the memristors to generate periodic (AC) output voltage spikes in response to a DC current or voltage input. This paper presents a steady-state analysis of dynamic neuristor models, including four-, five-, and six-state variables (each of which is a system of first-order ODEs involving the states) based on the original phenomenological model of the Mott memristor. Specifically, it reveals the unique stable operating points that occur for applied currents or voltages below the amounts needed to induce resistive switching. These DC operating points represent the physically meaningful “OFF” states for the circuit when the neuristor does not output voltage spikes. Jacques Hadamard's mathematical criteria for a well-posed physical model (existence, uniqueness, continuity, stability) motivated the search for these DC operating points (OFF states), which are needed for efficiently initializing neuristor models before conducting dynamic neuristor simulations. The key result of our analysis is the neuristor steady-state eq. (29) which is useful for understanding neuristor OFF states as well as the role of negative-differential resistance (NDR) in the operation of the Mott memristor model and neuristor circuits. In addition to the steady-state analysis, three numerical examples of dynamic neuristor circuit operation are also given and MATLAB code for the dynamic four-state model is available for interested readers.

Electromechanical performance of dielectric elastomer composites: Modeling and experimental characterization

Dielectric Elastomer (DE) devices have gained widespread attention in recent years for their ability to generate large, reversible strains in response to electric actuation. However, some DE materials exhibit a viscoelastic nature that detracts from their electromechanical performance in applications requiring precise time-dependent actuation. This study presents an investigation into the feasibility of using multilayered DE composites, comprising commercially available acrylic-based VHB 4905 and natural rubber membranes, to overcome the viscoelastic effects. A comparison of the electromechanical performance of bi-layer and tri-layer DE composites with that of a mono-layer VHB 4910 membrane is carried out through numerical and experimental methods. We present a theoretical model of the DE composite-based bulging actuator, using an energy-based approach and the assumption of homogeneous deformations. The model predicts the time-dependent deflection of the inflated/deflated multilayered DE composites, taking into account the effect of the intervening air column. The predictive capabilities of the model are validated through experiments under both DC and AC operating conditions, and the electromechanical performance of the DE composites is examined for various actuation responses such as resonance, creep, and hysteresis. The bi-layer DE composite is found to be superior in terms of actuation levels, reduced hysteresis, and reduced creep response. The findings of this study hold promise for the development of DE materials with improved actuation capabilities while maintaining dielectric breakdown strength.

DC operating points of nonlinear circuits and generalized Carleman linearization

PurposeThe purpose of this paper is to present a procedure for approximating DC operating points of nonlinear circuits. The presented approach can also be applied in case of multiple DC operating points.Design/methodology/approachA generalized Carleman linearization is used, which transforms an algebraic nonlinear equation into an equivalent infinite-dimensional linear system. In general, no close-form solution can be given for the infinite-dimensional linear system. Hence, the infinite-dimensional linear system is approximated by a finite one over a predefined interval using a self-consistent technique. The presented procedure allows to approximate all possible DC operating points within a predefined interval. To isolate all DC operating points, the initial interval is gradually divided into subintervals.FindingsIt is shown that the presented approach is not restricted to the polynomial case and allows to approximate all DC operating points. The presented approach can be applied in case of multiple DC operating points and does not depend on the domain of attraction of the DC operating points.Originality/valueA new procedure for the approximation of DC operating points of nonlinear circuits based on a generalized Carleman linearization is presented. This approach can be applied in case of multiple DC operating points and is independent of the domain of attraction. Further, this generalized approach is not restricted to the polynomial case and can be applied to a variety of circuits.

Numerical Optimization of the FFS Quadrupole

Three experiments HIHEX (Heavy Ion Heating and Expansion), LAPLAS (Laboratory Planetary Sciences) and PRIOR (Proton Microscope for FAIR) are proposed by the HED@FAIR (High Energy Density at Facility for Antiproton and Ion Research) collaboration to study matter under extreme conditions of temperature and pressure at the FAIR facility in Darmstadt, Germany. A special beam strong final focusing and imaging system has to be installed at the end of the HED@FAIR beam line. One of the main components of these systems are four wide-aperture quadrupoles, which have to provide a focal spot of about a millimeter size. Within the framework of collaboration between IHEP and GSI at IHEP, these magnets will be designed and produced. The main parameters of the quadrupoles are: DC operating mode; the coil inner diameter is 260 mm; the minimal distance between quadrupole centers of two nearby magnets is 2500 mm; the integral of field gradient is 66 T. The prototype of the quadrupole coil is manufactured and its mechanical characteristics is studied. The 2D and 3D geometry of large-aperture quadrupole is optimized taking into account these studies. The general characteristics of this geometry are presented in this article.

Impact of Bias Temperature Instabilities on the Performance of Logic Inverter Circuits Using Different SiC Transistor Technologies

All electronic devices, in this case, SiC MOS transistors, are exposed to aging mechanisms and variability issues, that can affect the performance and stable operation of circuits. To describe the behavior of the devices for circuit simulations, physical models which capture the degradation of the devices are required. Typically compact models based on closed-form mathematical expressions are often used for circuit analysis, however, such models are typically not very accurate. In this work, we make use of physical reliability models and apply them for aging simulations of pseudo-CMOS logic inverter circuits. The model employed is available via our reliability simulator Comphy and is calibrated to evaluate the impact of bias temperature instability (BTI) degradation phenomena on the inverter circuit’s performance made from commercial SiC power MOSFETs. Using Spice simulations, we extract the propagation delay time of inverter circuits, taking into account the threshold voltage drift of the transistors with stress time under DC and AC operating conditions. To achieve the highest level of accuracy for our evaluation we also consider the recovery of the devices during low bias phases of AC signals, which is often neglected in existing approaches. Based on the propagation delay time distribution, the importance of a suitable physical defect model to precisely analyze the circuit operation is discussed in this work too.

Extensive assessment of the charge-trapping kinetics in InGaAs MOS gate-stacks for the demonstration of improved BTI reliability

Gate-stack reliability has been a major roadblock in the realization of InGaAs-channel based logic technology. Excessive charge trapping in the gate-oxide causes time-dependent drift in transistor threshold voltage (Vth). The extent to which Vth drifts under certain stress conditions depends on (i) the defect ground-state energy distributions in the oxide bandgap, and (ii) the specific activation energy distributions for charge capture/emission process. In this work, semi-empirical modelling of ground-state defect energy distributions is revisited to determine the Total Operating Voltage Range of InGaAs-based MOSFETs for a DC-BTI lifetime of 10 years under DC operating conditions. Non-radiative Multiphonon (NMP) theory is subsequently used to describe the microscopic physics of charge (de-)trapping kinetics in terms of activation energy barriers for charge capture (EAc) and emission (EAe) into/from gate-stack defects. These activation energy barriers are visualized using Capture/Emission Time (CET) maps, which are efficient and powerful tools to predict the BTI degradation under different AC operating conditions as well. We demonstrate that the enhanced BTI reliability of a gate-stack with a novel ASM interfacial layer (ASM-IL), as compared to the bilayer gate-stack of Al2O3/HfO2, results from the favorable reconfiguration of the defect energy distribution in the oxide bandgap, as well as their activation energies for capture and emission process.

Ageing and reliability of electrical insulation: the risk of hybrid AC/DC grids

With an impetuous growth of DC links and future grids that will be often hybrid, providing AC and DC supply to nearby or the same customer, an important element is often neglected, that is, electrical insulation. There are no doubts that overhead lines will step back compared to insulated cables, for known reasons of environmental impact, right of way and reliability, especially in an urban or harsh environment. On the other hand, while AC insulation systems have been investigated and used for decades, there is no analogue experience for DC polymeric insulation, nor for insulation systems subjected to power electronics supply. This study aims at enhancing the attention on this topic, focusing on insulation ageing mechanisms and models of relevance for hybrid AC/DC assets and grids. Ageing and life models for AC, DC and power electronics supply are discussed and compared to experimental data, focusing on partial discharge and space charge. It is shown how these two phenomena affect lifetime for different AC, DC and transient operating conditions. The main drivers for insulation design and material selection are discussed, showing that insulation reliability can be achieved only if operating stresses, ageing mechanisms and life models are known and accounted for properly by insulation designers.

Quantifying Dynamic On-State Resistance of GaN HEMTs for Power Converter Design via a Survey of Low and High Voltage Devices

Designing and optimizing high switching frequency, ultra-efficient converters requires detailed knowledge of the behavior and parasitic parameters for both active and passive components. Recently, wide bandgap transistors have enabled simultaneous increases in both switching frequency and efficiency due to higher maximum operating junction temperature limits, lower dc on-state resistances, and reduced parasitic inductances and capacitances. Yet, the early acceptance of gallium-nitride (GaN) switches was plagued by detrimental dynamic on-state resistance effects. This complex phenomenon for GaN devices is characterized by deviations in on-state resistance from dc operating characteristics based on design choices such as the magnitude and duration of both voltage and current stress, switching mode, and junction temperature. While device manufacturers have made improvements compared to early generation devices, experimental evidence from a survey of commercial GaN transistors highlight measurable change in on-state resistance still exists due to variations in voltage stress during hard-switching operation. After sharing insights for obtaining low noise measurements, an analysis method along with two metrics are proposed to characterize dynamic on-state resistance measurements for power electronics designers. Quantifying the performance of GaN devices with standardized metrics facilitates a fair comparison between different GaN device technologies during converter development, enables manufacturing qualification for GaN switches, and provides a benchmark to catalyze improvement for the next generation of GaN device development.

Sizing CMOS Amplifiers by PSO and MOL to Improve DC Operating Point Conditions

The sizes of the metal-oxide-semiconductor (MOS) transistors in an operational amplifier must guarantee strong direct current operating point (DCOP) conditions. This paper shows the usefulness of two population-based optimization algorithms to size transistors, namely—particle swarm optimization (PSO) and many optimizing liaisons (MOL). Both optimization algorithms link the circuit simulator SPICE to measure electrical characteristics. However, SPICE provides an output-file indicating that a transistor is in strong inversion but the DCOP can be in the limit, and it can switch to a different condition. In this manner, we highlight the application of PSO and MOL to size operational transconductance amplifiers (OTAs), which DCOP conditions are improved by the introduction of a procedure that handles constraints to ensure that the transistors are in the appropriate DCOP. The Miller and RFC-OTA are the cases of study, and their sizing is performed using UMC 180 nm CMOS technology. In both OTAs, the objective function is the maximization of the gain-bandwidth product under the main constraint of guaranteeing DCOPs to improve two figures of merit and to provide robustness to Monte Carlo simulations and PVT variations.

Numerical analysis of thermo-electric field for AC XLPE cables with different service times in DC operation based on conduction current measurement

This paper presents an estimate for the influence of service time on the conduction current characteristics of a 10 kV AC XLPE. The experimental conduction current results show that the space charge accumulation threshold increases with service time. Fourier transform infrared (FT-IR) and differential scanning calorimetry (DSC) experiments show increased thermo-oxidative aging and reduced crystallinity as the service time increases. This results in deeper traps in the XLPE material which can be verified from isothermal surface potential decay experiments. Based on the experimental results, the numerical analysis of thermo-electric fields is carried out for 10 kV AC XLPE cables with different service times under bipolar DC operation mode. It shows that the DC power for 10 kV AC XLPE cable in bipolar DC operation is higher than the AC power, whereas the DC operating voltage and DC power increases with the service time. In order to ensure a safe and long service life of the cables in DC operation, a conductor temperature of 60 °C and DC operating voltage of 11 kV are recommended for 10 kV AC XLPE cables in bipolar DC operation.

Thermo‐electric field analysis of AC XLPE cable in monopole, bipole, and tripole DC operation modes

This paper presents a numerical analysis of thermo-electric fields of 10 and 35 kV AC XLPE cables in monopole, and tripole DC operating modes based on conduction current measurements. DC conductivities and electric field thresholds of the space charge accumulation for XLPE materials were estimated at different temperatures and electric fields. The result showed that the electric field threshold of the space charge accumulation for the materials reduced with an increase of the temperature. DC currents of the cables were increased with the increase of the operating temperatures in the three DC operation modes. The maximum DC operation voltage of the cables increased with the decline of the operation temperature in the three DC operation modes. The maximum transient electric fields were below the threshold of the space charge accumulation for the cables in the tripole DC operation. The maximum transmission power of the 10 kV XLPE cable in the DC operation modes was at 60°C, whereas the maximum transmission power of the 35 kV XLPE cable was at 50°C. It was elucidated that the 10 kV AC XLPE cable could have more advantages than the 35 kV AC XLPE cable in the three DC operation modes.

Modeling and optimization of gaseous helium (GHe) cooled high temperature superconducting (HTS) DC cables for high power density transmission

Superconducting cables are considered a viable technology to meet the increasing global demand of electricity transmission and distribution. This paper presents a transient mathematical model to predict the thermal response of a superconducting cable contained in a flexible cryostat. The model was conceived to be computationally fast so that system response according to variations of physical properties of the materials, and operating and design parameters could be assessed for optimization purposes. A volume element method (VEM) was utilized, which resulted in a system of ordinary differential equations with time as the independent variable. The model is also space dependent, through the establishment of a mesh with a known three-dimensional distribution of the volume elements in the computational domain. Pressure drop in the gas channels and the temperature gradient with respect to space in the flow direction were taken into account. The numerically calculated DC cable heat leak rate under different environmental conditions was initially adjusted and then experimentally validated by direct comparison to actual experimental data. The final part of the study consisted of using the experimentally validated model to perform the DC cable design and operating parameters optimization in order to obtain minimum heat leak rate and pumping power (or total consumed power). By adopting a fixed cable cross sectional area constraint (or total volume for a given length), an optimized helium channels geometry is also found that shows significant improvement in system performance in comparison to an existing system geometry. For example, for a GHe mass flow rate of 3.8 g s−1, the cryostat with the original geometry is shown to consume 20.5% more power than with the optimized geometry. As a result, it is reasonable to state that the combination of accuracy and low computational time allow for the future utilization of the model as a reliable tool for HTS DC cable & cryostat simulation, control, design and optimization purposes.

Exploring a Novel Methodology for DC Analysis in Memristive Circuits with Multiple Operating Points

The memristor and the memristive systems have represented a challenge to be incorporated into a simulation procedure in order to carry out novel applications. The discovery of the physical memristor by the HP Labs has caused widespread interest for modeling the memristive behavior in order to combine this new fundamental circuit element with traditional devices. DC domain analysis represents a fundamental stage in the circuit simulators because the DC operating points are used as starting points in other analysis domains. In this work, the DC response of mathematical memristive systems is explored in order to recognize different scenarios according to the nature of the memristive variable. The piecewise linear formulation has been used in order to establish the memristive phenomenon in the device. As a result of this exploration, a novel DC modeling methodology for memristive systems is introduced. This methodology is capable of generating current–voltage branch relationships that represent the memristive behavior of the device. The memristive model proposed is characterized in order to determinate the impact of the variables on the memristive behavior. Moreover, the existence of multiple DC operation points (MOPs) is treated and the conditions for the occurrence of MOPs are established by two cases of study. Finally, the new contributions of this work compared to previous work are presented and discussed.

Improved Two-Level Voltage Source Converter for High-Voltage Direct Current Transmission Systems

This paper presents an improved two-level voltage source converter for dc transmission systems with relatively low rated power and dc operating voltage. Unlike conventional two-level converter, the presented converter employs two distributed cell capacitors per three phase; thus, do not contribute any current when converter is blocked during dc short-circuit fault as in modular multilevel converter case. The use of three-phase cells is proven to be beneficial because the arm currents do not contain second-order harmonic currents, and cell capacitors tend to be small as they only experience high-order harmonic current associated with the switching frequency. For the same rated dc-link voltage and switching devices, the rated power of the improved two-level converter will be twice than that of the conventional two-level converter. Averaged, switching function, and electromagnetic transient simulation models of the improved two-level converter are discussed and validated against detailed switch model. The viability of the improved two-level converter for high-voltage dc applications is examined, considering dc and ac short-circuit faults. Besides, reduced complexity of the control and power circuit of the improved two-level converter, it has been found that its transient responses to ac and dc faults are similar to that of the modular multilevel converter.

Measurement of Core Losses in Electrical Steel in the Saturation Region under DC Bias Conditions

This paper presents a method to measure and determine core losses in electrical steel for high flux densities under dc bias conditions for electric machine applications. Test conditions require ac flux on top of dc flux, which can saturate the system. It is desirable to have a test system that would generate high flux densities without increasing the size of the ac power supply. We propose an innovative core tester that can handle the power requirements of the magnetic circuit formed by the test specimen. The dc and ac operating requirements of the magnetic circuits are separated and individual components are combined in such a way that a dc bias is provided from the slowly varying high-power component and the ac field is supplied by the low-power high-bandwidth component. The proposed topology consists of ac and dc blocker filters that provide separate pathways for the ac and dc currents. Circuit simulations and experimental test results are presented to verify the effectiveness of the proposed system.

Main Circuit Parameters Design of DC Operating Power Supply based on Electric System

The phase-shifted full bridge zero voltage soft switch (ZVS) topology of 2.2KW electric operation power supply is analyzed in brief. Then, parameters of main circuit are designed and selected. At the same time, the high frequency transformer and the oscillatory inductor are manufactured. According to the actual characteristics of electric power supply, the power MOSFET and the second rectifier-diode are chosen. By waveform analysis, temperature and power efficiency test, the experimental results confirm the reasonableness of the design.

Electric field analysis on the insulation design of the stop joint box for DC HTS power cable

DC HTS power cable is a promising electric power transmission line for the future of smart grid, and it has been competitively investigated at many research institutes all over the world. For the commercialization of DC HTS cable, higher power transmission capacity and longer length for long distance transmission line should be prepared. In order to meet the needs of long distance DC HTS cable, a joint box should be developed for the connection of cable components. As for AC HTS cable, a number of patents of nominal joint box have been already reported. However, any conceptual designs of the joint box for DC HTS cable have not been suggested yet. One of the reasons is that the cryogenic high voltage insulation design, especially in DC environment is not fully investigated yet. Conventional normal joint box for AC HTS cable could not be directly applied to DC HTS cable because different electric field distributions compared to AC electric field which requires totally different electrical insulation design concepts. In this paper, in order to establish the basic insulation design of the stop joint box (SJB) for DC HTS cable, three kinds of SJB models were designed and electric field analyses have been conducted both considering AC and DC environment. And the critical factors affecting the DC insulation design of the stop joint box were analyzed. From the simulation results, it was observed that the electric field distribution was totally different both in AC and DC operating conditions. And it was possible to find the weakest regions in the insulation design of the SJB. Consequently, based on the DC electric field analysis, the insulation design criteria and the desirable configurations were suggested for the insulation design of the stop joint box for DC HTS cable.

Control of DC-Fault-Resilient Voltage Source Converter Based HVDC Transmission System under DC Fault Operating Condition

Voltage source converter (VSC)-based high-voltage direct current (HVDC) transmission systems have attractive advantages compared to classical thyristor-based HVDC transmission systems. However, VSC-based HVDC transmission systems are vulnerable to dc side fault, and expensive dc circuit breakers are required to protect them against dc fault. This paper proposes a control method of a dc fault-resilient VSC which can be protected against dc fault without using expensive dc circuit breakers. In the VSC configuration, several H-bridge modules are connected in cascade, so the voltage balancing control of several floating dc capacitors is required. In this paper, an appropriate control structure with the capacitor voltage balancing controller is proposed. The appropriate control algorithm for dc fault operation and recovery after dc fault is also proposed. PSCAD simulation results are presented to validate the proposed control structure under normal and dc fault operating conditions. Real-time-digital-simulator results are also presented to verify the control structure.

Graphene Base Transistors: A Simulation Study of DC and Small-Signal Operation

A simulation study aimed at investigating the main features in dc and small-signal operating conditions of the hot-electron graphene base transistor (GBT) for analog terahertz operation is presented. Intrinsic silicon is used as reference material. The numerical model is based on a self-consistent Schrodinger-Poisson solution, using a 1-D transport approximation and accounting for multiple-valley and nonparabolicity band effects. Some limitations in the extension of the saturation region and in the output conductance related to the finite quantum capacitance of graphene and to space charge effects are discussed. A small-signal model is developed that catches the essential physics behind the voltage gain and the cutoff frequency, which shows that the graphene quantum capacitance severely limits the former but not the latter. According to simulations carried out within the ballistic transport approximation, a 20-nm-long GBT can achieve at the same time a voltage gain larger than 10 and a cutoff frequency largely above 1 THz within a reasonably wide bias range.

AlGaN/GaN HEMT Degradation: An Electro-Thermo-Mechanical Simulation

We present fully self-consistent simulation results based on an electro-thermo-mechanical model of a typical AlGaN/GaN HEMT structure. The mechanical stress state is analyzed under different dc operating conditions in view of possible dislocation formation and movement by comparing simulated elastic energy densities and resolved shear stresses with theoretically predicted values. In particular, we find nonzero resolved shear stress on all wurtzite slip systems, with relevant values especially at high dc power. This could allow formation and movement of dislocations, leading to device degradation.