DBC Substrate Research Articles

Role of graphene surface coating of DBC substrate on sintering motion behavior of copper nanoparticles for silicon carbide power devices

Role of graphene surface coating of DBC substrate on sintering motion behavior of copper nanoparticles for silicon carbide power devices

Concepts for realizing High-Voltage Power Modules by Embedding of SiC Semiconductors

Today’s power electronics modules typically consist of a ceramics substrate (DBC – Direct Bond Copper), carrying IGBTs, diodes or MOSFETs. These semiconductors are soldered or sintered to the ceramics and their top sides are interconnected by thick Al wires. An integration of further components or functions on the DBC substrate is difficult or even not possible. Therefore, driver circuits and controllers have to be mounted to a separate substrate, typically an organic Printed Circuit board (PCB). The PCB has to be connected to the DBC by wires or pins. The mechanical integration of the whole system requires a bulky housing. Embedding of power semiconductors like SiC MOSFET allows a significant size reduction, improved electrical performance and a high degree of reliability of such modules. In the last years, the capability of PCB embedding technology for the realization of low and high voltage power modules was demonstrated. Fraunhofer IZM together with partners from the industry demonstrated the feasibility for different applications, from single die SiC packages to high voltage automotive traction inverters. In this paper, a general overview about innovative power module technologies will be given and the embedding of power semiconductors will be introduced in detail. It will address all most relevant point, like the demands on the semiconductor, the thermal and electrical considerations as well as the demands on the used materials. To address the integration of the required driver circuits and controllers, the idea of modularization such electronics systems will also be presented. Here already packaged components will be used and embedded into PCB layers too. As a result, a modular approach to form a complete system will be developed. Different functional layers, e.g. power switches, logic modules, will be formed and finally stacked und connected to form the system. The concept and first realized demonstrators will be discussed.

Development of high thermal conductivity of Ag/diamond composite sintering paste and its thermal shock reliability evaluation in SiC power modules

Diamond has the highest thermal conductivity among naturally occurring materials and a relatively low coefficient of thermal expansion (CTE), making it a promising interconnected material for next-generation semiconductor power devices. In this study, Ag/diamond composite sintering paste was developed. The agglomerated diamond particles were uniformly dispersed in the sintered Ag porous structure, and the thermal conductivity was increased from 171.4 W/(m·k) for pure Ag sintering to 288 W/(m·k) for an Ag@2%diamond (2% of the total weight of Ag) specimen. The interfacial microstructure evolution and fracture behavior were investigated in detail for a SiC/Direct Bond Copper (DBC) joint structure during an extreme thermal shock test (TST) in the range of −50 °C–250 °C. Importantly, with a moderate amount of diamond additive, the microstructural degradation and severe deformation of the DBC substrate were effectively suppressed. This is mainly attributed to the diamond addition, which can block the migration pathways of Ag atoms toward long-term thermal shock and adjust the thermo-mechanical performance of the sintered layer. This detailed study about Ag/diamond composite paste can provide new guidance for strengthening sintered Ag interconnections for SiC power modules.

Degradation Behavior of High Power Semiconductor Modules by Low-Temperature Sintering Technology

This paper presents a degradation behavior of high-power semiconductor modules, i.e., IGBT, with sintered silver by power cycle test and thermal cycle test. The electrical characteristics, such as on-state voltage drop, thermal resistance and leakage current, were studied. For power cycle test, the IGBT module still has an acceptable electrical performance after the 30 K power cycles. No noticeable changes can be found in the die-attach layer, while the DBC-attach layer begins to fail after 30 K power cycles. For the thermal cycling test, the electrical characteristics of the IGBT module were only tested within the first 300 cycles because the Al2O3 DBC substrate failed first before the failure of the bonding layers. Finally, finite element methods (FEM) were used to analyze thermal and mechanical stress distribution and failure mechanism of the bonding layers.

Microstructural evolution, fracture behavior and bonding mechanisms study of copper sintering on bare DBC substrate for SiC power electronics packaging

Robust bonding of Cu quasi-nanoparticles sintering for Ag coated chip and bare copper substrate was achieved. The effect of temperature, pressure and time on the sintering bonding strength and microstructural evolution was deeply studied. 36.5 MPa shear strength was achieved when applied 5 MPa pressure. By increasing to 30 MPa, it shows the best die shear strength of 116 MPa, accomplished with a sintering temperature of 250 °C for 3 min. Temperature also influenced the shear strength a lot. Between 210 °C and 230 °C can already provide strength over 30 MPa. When increased to 270 °C, the strength was extremely enhanced to over 120 MPa. Inspection on the fracture behaviors and cross-section of sheared off samples was conducted by SEM, EDS, and XRD. It is found that low bonding performance is due to both of the incomplete burnt out of organics and incomplete Cu QNPs sintering. In addition, high bonding is account for the positive effect of pressure and temperature on promoting the necking growth, sintering networking formation, pores isolation and brittle-ductile fracture transformation. The recommended sintering profile is 250 °C, 3 min, 20 MPa. Finally, the feasibility for SiC MOSFET power electronics DA was verified by testing its static characteristics at both room temperature and 150 °C.

Pressureless Sintered-Silver as Die Attachment for bonding Si and SiC Chips on Silver, Gold, Copper, and Nickel Metallization for Power Electronics Packaging: The Practice and Science

Low-temperature silver (Ag) sintering is emerging as a cutting-edge die-attach technology for power electronics packaging. However, the industry still has concerns about completely accepting this technology. One of the reasons is a lack of knowledge about the mechanism and process of sintered silver bonding on various metallization. Before, we reported a preliminary assessment of the die-shear strength and microstructures of Si dummy device attached on Ag, Au, and Cu metallization. This research will go deeper into the practice and science of attaching Si and SiC devices with sintered-Ag on substrates with up to seven most widely used metallizations, including electroplated Ag, Ni/Au, and Ni, electroless-plated Ni(P)/Ag, Ni(P)/Au, and Ni(P), and native Cu on DBC substrate. All sintered-Ag die-attach were pressureless in the air at temperatures ranging from 220 °C to 300 °C. The mechanical, electrical, and thermal parameters, as well as the microstructural analyses, were assessed. The purpose of this research is to gain a better understanding by: 1) discussing effects of devices and substrate metallizations on the mechanical, electrical, and thermal characteristics; 2) reviewing fundamental mechanisms of interfacial adhesion for sintered-Ag bonding, and 3) providing practical considerations for developing Si and SiC sintered-Ag die-attaching profiles on the widely used substrate metallization.

Solid-Liquid Interdiffusion Bonding between Ti/Ni/Ag/Sn Backside Metallized Si Chips and Cu/Al2O3 - DBC Substrates with Au/Pd/Ni Surface Finish

Solid-Liquid Interdiffusion Bonding between Ti/Ni/Ag/Sn Backside Metallized Si Chips and Cu/Al₂O₃ - DBC Substrates with Au/Pd/Ni Surface Finish

Study of Thermal Stress Fluctuations at the Die-Attach Solder Interface Using the Finite Element Method

Solder joints in electronic packages are frequently exposed to thermal cycling in both real-life applications and accelerated thermal cycling tests. Cyclic temperature leads the solder joints to be subjected to cyclic mechanical loading and often accelerates the cracking failure of the solder joints. The cause of stress generated in thermal cycling is usually attributed to the coefficients of thermal expansion (CTE) mismatch of the assembly materials. In a die-attach structure consisting of multiple layers of materials, the effect of their CTE mismatch on the thermal stress at a critical location can be very complex. In this study, we investigated the influence of different materials in a die-attach structure on the stress at the chip–solder interface with the finite element method. The die-attach structure included a SiC chip, a SAC solder layer and a DBC substrate. Three models covering different modeling scopes (i.e., model I, chip–solder layer; model II, chip–solder layer and copper layer; and model III, chip–solder layer and DBC substrate) were developed. The 25–150 °C cyclic temperature loading was applied to the die-attach structure, and the change of stress at the chip–solder interface was calculated. The results of model I showed that the chip–solder CTE mismatch, as the only stress source, led to a periodic and monotonic stress change in the temperature cycling. Compared to the stress curve of model I, an extra stress recovery peak appeared in both model II and model III during the ramp-up of temperature. It was demonstrated that the CTE mismatch between the solder and copper layer (or DBC substrate) not only affected the maximum stress at the chip–solder interface, but also caused the stress recovery peak. Thus, the combined effect of assembly materials in the die-attach structure should be considered when exploring the joint thermal stresses.

Field Grading Composites Tailored by Electrophoresis—Part 2: Permittivity Gradient in Non-Uniform Electric Field

A series of three articles present an innovative way to build advanced functionally graded materials (FGM) based on polymer/ceramic composites tailored by electrophoresis from the process principle to their field grading application in power electronics. In this Part 2, it was studied the impact of a non-uniform electric field on the high-k SrTiO3 particle organization within an epoxy matrix. In that purpose, DBC substrates with sharp metallization tracks were used to generate a strong electric field divergence. This non-uniform field has been used to organize the particles around the field reinforcement regions during the electrophoresis process. It was discovered that the particles self-arrange into a conformal composite FGM layer that presents a local permittivity gradient: the highest ε being located around the electric field peak areas. This new process could be used to selectively `heal' the electric field-induced weaknesses of any high voltage electrical system by using its own design.

Field Grading Composites Tailored by Electrophoresis—Part 3: Application to Power Electronics Modules Encapsulation

A series of three articles presents an innovative way to build advanced functionally graded materials (FGM) based on polymer/ceramic (epoxy/SrTiO3) composites tailored by electrophoresis for field grading in power electronics. In Part 3, this method is applied in the context of power modules for DBC substrate encapsulation. An evaluation of the FGM performances is reported based on electrostatic simulations and breakdown voltage measurements on encapsulated DBC substrates. The results show a significant mitigation of the electric fringe field at the triple point while breakdown is largely increased by a factor 2 for FGM composites compared to neat epoxy. The process enables the use of electric field reinforcements of HV electrical systems (e.g. tips coming from the design), and thus potential weak points, to locally `self-heal' them in-situ. Such an electrophoresis process used to build FGM composites paves the way for the next generation of functionalized polymer composites used in high voltage power applications for improving the electrical aging of insulating materials and power system reliability.

Large-Area Substrate Bonding With Single-Printing Silver Paste Sintering for Power Modules

Sintered silver with high thermal conductivity and reliability has been considered as a promising substrate bonding solution in power modules. The traditional double printing process is complex, and the second layer of silver paste is too thin to ensure complete wetting. We greatly simplified the sample preparation process by single printing and optimized the sintering process by means of open-face contact drying technology and staged heating method. In this article, the effect of predrying steps and heating rate on the quality of sintered silver joint on large area silver-plated DBC substrate and its mechanism are discussed. The microstructure shows that the samples sintered by the optimized sintering process have no obvious defects, and the sintered silver layer is dense and uniform. In order to evaluate the bonding quality of the whole joint, the sample was cut into 16 small pieces by metallographic cutter, the average shear strength was 55.65 MPa, and the strength distribution between the center and the edge of the sample was uniform. The samples sintered by an optimized sintering process show cohesive failure mode and typical ductile fracture morphology. The energy dispersive spectrum analysis shows that the composition distribution of the sintered silver layer in the center and edge of the sample was relatively uniform, which is consistent with the distribution of shear strength. The scanning electron microscopy image of cross section demonstrated that the porosity of the adhesive layer is 3.08%, which is far lower than that of the traditional double printing process, with good interface bonding and no delamination.

Design, Analysis, Comparison, and Experimental Validation of Insulated Metal Substrates for High-Power Wide-Bandgap Power Modules

Abstract Direct bonded copper (DBC) substrates used in power modules have limited heat spreading and manufacturing capability due to ceramic properties and manufacturing technology. The ceramic and copper bonding is also subject to high mechanical stress due to coefficient of thermal expansion mismatch between the copper and the ceramic. For wide-bandgap (WBG) devices, it is of interest exploring new substrate technologies that can overcome some of the challenges of direct bonded copper substrates. In this technical paper, the design, analysis, and comparison of insulated metal substrates (IMSs) for high-power wide-bandgap semiconductor-based power modules are discussed. This paper starts with technical description and discussion of state-of-the-art DBC substrates with different ceramic insulators such as aluminum nitride (AlN), Al2O3, and Si3N4. Next, an introduction of IMSs and their material properties, and a design approach for SiC (silicon carbide) metal-oxide-semiconductor field-effect transistor (MOSFET)-based power modules for high-power applications is provided. The influence of dielectric thickness on the power handling capability of the substrate are also discussed. The designed IMS and DBC substrates were characterized in terms of steady-state and transient thermal performance using finite element simulation. Finally, the performance of the IMS and DBC are validated in an experimental setup under different loading and cooling temperature conditions. The simulation and experimental results showed that the IMS can provide high steady-state thermal performance for high-power modules based on SiC MOSFETs. Furthermore, the IMS provided enhanced transient thermal performance, which provided a reduced junction temperature when the module is operated at low fundamental output frequencies in traction drive systems.

Lifetime Model for the Fatigue Fracture in Cu/Al2O3/Cu Composites: Experimental Validation of a Substantial Lifetime Enhancement by Cu Step Etching

AbstractDirect bonded copper (DBC) alumina (Al2O3) substrates are used in power electronic devices in order to transfer the heat from semiconductor devices to the heat sink and to carry high electric currents. Fatigue-induced cracks in the ceramic result in a diminished heat dissipation, leading to failure of a power device. Hence, a lifetime model concerning this failure mode is necessary. In this paper, a new lifetime model including crack initiation as well as crack propagation for the fatigue fracture of Al2O3-based DBC substrates is presented. It is based on experimental crack detection techniques and finite element method (FEM) simulations including fracture mechanics. For the validation of the lifetime model, experiments are presented which show that by appropriate design of the copper edge, the lifetime of the substrates is increased substantially.

Reliability analysis of bonding wire based on stacked substrate packaging structure

Abstract The stacked substrate packaging technology is a new 3D power loop structure utilizing multiple layer DBC to achieve ultra-low parasitic for the fast switching SiC device. This structure has a different geometry on interconnection between chips and substrate contrasting to the conventional module design, which needs optimization on the interconnection for the reliability consideration of this new structure. Analytical models of different bonding wire shapes and DBC structures were developed to calculate the von-mise stress on each model under thermal cycling simulation. The simulation results show that the stress on bonding wire reaches minimum when welding point located at the center of the top DBC substrate and the stress decreases when DBC top copper layer thickness increases or ceramic layer thickness decreases. Moreover, bonding wires with smaller diameter, certain peak height and width show lower stress and strain. Furthermore, thermal cycling tests were done on samples with same geometries of analytical models, and the wire pull test results showed consistency with the stress calculation results which verifying the optimum wire shape and DBC structure for the stacked substrate packaging.

Reliability analysis of sintered Cu joints for SiC power devices under thermal shock condition

In this study, the thermal shock reliability of sintered Cu joints on SiC power device application was investigated. Firstly, sintered Cu joints were used to bond chips and substrate consisting of various materials to evaluate their bondability. Secondly, SiC dummy chips were bonded to DBC substrate and thermal shock test from −40 °C to 250 °C were performed both in the ambient atmosphere and in vacuum. Finally, the SiC MOSFETs bonded by sintered Cu joints were evaluated by power cycle test from 25 °C to 200 °C and the thermal conductivity was evaluated by T3ster equipment. The results showed the sintered Cu exhibited extremely high reliability during the thermal shock aging test in ambient atmosphere although inferior reliability was observed in vacuum. This phenomenon was investigated and explained by field-emission scanning microscope, energy-dispersive X-ray spectroscopy, and X-ray diffractometer.

Влияние топологии многокристальных IGBT-модулей на распределение тока между транзисторными чипами в статических режимах работы

Factors affecting the distribution of direct current among parallel transistor chips in a multichip IGBT module are experimentally investigated. The voltage-current characteristics (VCCs) of single-chip modules with the rated operating current equal to 200 A and voltage equal to 1200 V in the collector current range from 50 to 200 A at temperatures equal to 25, 90, 120 and 150°C were measured to evaluate the compensation ability of the saturation voltage positive temperature dependence. A comparative experiment on measuring the voltage drop across individual parts of the conductors system composed of samples of IGBT modules with different topologies based on the half-bridge circuit arrangement and having three parallel-connected chips in passing a 400 A direct current through the module was carried out. It has been found from the experimental results that the use of the saturation voltage positive temperature dependence for equalizing the current distribution between the chips has limited capabilities, and that one of possible methods for achieving this is to use the resistance of a system of aluminum conductors. Comparative tests were carried out for estimating the stability of modules with different topologies to the effect of cyclic current load in a mode facilitating accelerated degradation of the soldered seam between the chip and the DBC substrate. The experimental results confirm the importance of considering the factors affecting the static current distribution between the chips in designing the topology of multichip IGBT modules.

Shear Strength and Thermomechanical Reliability of Sintered Ag Joints Containing low CTE Non-metal Additives for Die Attach

Abstract Ag sintering has been paid attention as an alternative to soldering in die attach for decades, especially for high temperature power electronics packages because of its high melting temperature, highly thermal and electrical conductivity of the sintered silver joints, and low process temperature less than 275°C. The coefficient of thermal expansion (CTE) of silver (19.1ppm/°C), however, is much higher than the silicon die (2.6ppm/°C) and the commonly used alumina substrate (7.2ppm/°C). CTE mismatch of the different materials in the various components in a power electronics package lead to the delamination at the interface between interconnection layer and chips or substrate, and/or cracking of the interconnection layer is one of the mostly common causes of failure of power electronics device during thermal cycling or high temperature operation. In recent years we have been developing a series of silver sinter pastes containing low CTE non-metal particles to reduce or adjust CTE of the sintered joints so as to extend the lifetime and reliability of power electronics device in high temperature applications. In the present paper, we will report a new set of silver sinter pastes containing micro scale non-metal particles, a sintering process, microstructural morphologies, thermo-mechanical reliability of the sintered joint and effect of the contents of non-metal particles on shear strength of the sintered silver joints bonding an Ag silicon die on Ni/Au DBC substrates. Shear tests on the sintered joints with and/or without the low CTE non-metal additives have been conducted at room temperature, 200, 250, and 300°C. Thermo-mechanical reliability of the sintered joints was evaluated by thermal cycling, thermal shock, high temperature storage tests (HTS), respectively. X-ray inspection and scanning electronic microscopy (SEM) were used to characterize void, crack and microstructure morphologies of the sintered joints with and/or without the additives.

Non-destructive imaging of defects in Ag-sinter die attach layers – A comparative study including X-ray, Scanning Acoustic Microscopy and Thermography

In typical power electronic modules several semiconductor dies such as MOSFET or IGBT are soldered to a DBC substrate. During module production the quality of the solder layers can be monitored by the use of X-ray inspection and the void rate can be determined. Recently, the more robust Ag-sinter technology is deployed for attaching the power dies to the substrate, especially for high reliability or high temperature requirements. Besides voiding also adhesion problems can occur during sintering due to multiple reasons (e.g. contamination). In contrast to volume defects, pure adhesion problems cannot be detected by means of X-rays. Accordingly, other methods have to be applied for process monitoring. The present investigation compares the advantages and disadvantages of different non-destructive imaging techniques towards the detection of defects in sinter layers. Besides X-ray, Scanning Acoustic Microscopy (SAM) and Lock-in Thermography methods (DLIT + ILIT) were studied and evaluated in terms of suitability for detecting different defect types, resolution (minimum defect sizes), inspection time and possible integration into the assembly process.

Development of thermal shock-resistant of GaN/DBC die-attached module by using Ag sinter paste and thermal stress relaxation structure

GaN die-attach/DBC substrate joint structure bonded by Ag sinter paste/W thin film/Ag sinter paste sandwich die-attached layer was designed and its high-temperature reliability was investigated. GaN chips were bonded to DBC substrate using Ag sinter paste with thin W film at 220 °C and at 0.4 MPa for 60 min. The joints structure was subjected to thermal shock testing in temperature range of −50 to 250 °C for duration up to 1000 cycles. The initial average die shear strength of the GaN/DBC joint structure was about 30 MPa, and was maintained up to 1000 cycles. These results reveal that Ag sinter paste/W thin film/Ag sinter paste sandwich die-attached layer can provide a superior thermal shock resistant. The microstructure evolution of GaN/DBC joint structure during the thermal shock testing was observed by FE-SEM and EDX analysis. In addition, FEM numerical simulation has also been implemented in this study, which revealed that the GaN/DBC joint structure with the sandwich die-attached layer shows a stress-shielding effect from the external force, and thus achieves a reliable power module structure for wide-bandgap semiconductors for its application in high-temperatures.

(Invited) Packaging Material Technology for Wide Band Gap Power Devices and Its Performance/Reliability Evaluation

Wide band gap semiconductors such as SiC and GaN have been expected to be established as the next generation power semiconductors, which are capable to reduce huge energy-loss in electric power conversion. The application of them will increase power density resulting in operation temperature rise beyond 200 °C. In addition, both increase of current and of frequency will also increase stress on devices. In general, power devices must possess robustness and high reliability for safe control of power conversion. Heat dissipation from the hot die in operation is one of the essential key factors for establishing high performance WBG devices. Here we report the current status of high temperature packaging materials including die-attach, wiring, substrates and molding compounds. In addition, reliability issues including thermal shock, power cycling and transient thermal properties will be summarized. A series of DBC and DBA substrates, composed of Al and Cu as metal layers and of Al2O3, AlN and Si3N4, were examined by thermal shock test between -50 °C and 250 °C. DBC substrates with Al2O3 and AlN fractured only after 10 cycles due to severe thermal stress while all DBA and DBC with Si3N4 substrates survived. Al and Cu layer of all DBC and DBA substrates severely deformed by thermal shock. By microstructural observation, grain boundary sliding during thermal shock has a key to cause deformation of metal layers on ceramics. Ni and Ni-P plating on metal layer also deformed followed by Al and Cu layer deformation. Ni-P plating showed severe cracking which can be attributed to brittleness of Ni-P plating while Ni plating did not. Ag sinter joining can be successfully applied for die attach by low temperature and low pressure bonding in air. For better bonding quality, Ag coating is the best metallization due to the specific reaction of Ag in air. By modifying solvent, Ag particles paste was modified to form a good bonding with Au surface finish. It can provide not only high temperature structural stability but also excellent thermal dissipation capability. High die-shear strength beyond 30 MPa was maintained by thermal shock between -50 °C and 250 °C up to 1000 cycles for a DBC die-attach structure. The thermal resistance of Ag sinter joined die attach is much lower than that of solder. Figure shows the example of a GaN die-attached on DBC substrate with a new Ag sinter materials at 200 °C in air without any pressure. Even on the Au metallization, the GaN die was bonded with high strength. The interface shows a good bonding between Au and Ag. This work was supported both by JST ALCA project on GaN packaging and by METI standardization project for evaluation methods of thermal properties of ceramics substrates. Figure 1