dB SNDR Research Articles

A 62.5 kHz-BW 92 dB-SNDR noise-shaping SAR ADC with NS-CAL method

DAC mismatch is a significant error in NS-SAR ADCs, as it introduces essentially nonlinear behavior and limits the number of bits in the DAC array. In this paper, we propose a novel foreground digital calibration method for NS-SAR ADCs. This method, combined with noise shaping technique, improves calibration accuracy and eliminates the impact of error accumulation on high-bit weights. Thus, it increases the number of bits in the DAC array in NS-SAR ADCs, and decreases the noise floor caused by quantization error. We implemented this design using a 110-nm CMOS process. As a result, post-layout simulation shows 92 dB SNDR and 108 dB SFDR under × 16 OSR and 1.5 V supply. Compared with conventional foreground calibration method, the SNDR increases from 81 dB to 92 dB and the SFDR increases from 84 dB to 108 dB with a power consumption of 40 μW, resulting in a FoMs of 182 dB and a FoMw of 15.3 fJ/conversion-step, respectively.

A 10-bit 70-MS/s SAR ADC with Reference Buffer in 40nm CMOS

Abstract A 10-bit 70-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) with reference buffer is presented in this paper. Segmented capacitive DAC with redundant 2bits is designed to relax the design of reference buffer. A hybrid switching sequence is applied to the ADC to optimize power consumption. The Measurement results Show that the core SAR ADC achieves 48.52 dB SNDR and 56.67 dB SFDR at 70 MS/s sampling rate and Nyquist input frequency, consuming 2.50mW power consumption, achieving a FoM of 163.6 fJ/step. The ADC occupies an active area of 0.017 mm2 in 40nm CMOS technology.

A 18-bit 1-MS/s fully-differential SAR ADC with digital calibration achieving 96.1 dB SNDR

This paper presents a 18-bit 1 MS/s fully-differential Successive-Approximation-Register Analog-to-Digital Converter (SAR ADC) achieving an ENOB of 15.7-bit. To achieve higher performance, a differential DAC utilizing both split and monotonic switching timing is designed. For both dynamic and static performance improvement, five techniques are proposed. First, a foreground digital self-calibration method based on normalized-full-scale-referencing is described to eliminate the capacitor mismatch errors. L-segment capacitors are utilized to measure and calculate the bit weights of other capacitors. Second, a DNL enhancement technique is presented. The fractional capacitors are used to subtract an analog voltage from the DAC before the conversion is finished, which further improve the ADC performance. Third, an adaptive-tracking-extra-bit-trail together with comparator noise extraction and correction for further accuracy enhancement is proposed. Forth, a harmonic calibration technique, which can efficiently attenuate 2-order and 3-order harmonic is introduced. Fifth, a comparator with ultra-low noise and offset is designed to meet the 18-bit 1-MS/s ADC. The ADC is fabricated in a 0.18-μm 5-V CMOS process. It measures a 96.1 dB SNDR and a 110.7 dB SFDR. The DNL and INL are within ±0.32 LSB and ±0.5 LSB, respectively. The overall power consumption of ADC core, drawn from the 5 V power supply, is 45 mW.

Power-efficient 12-bit 800 MS/s voltage-time hybrid domain ADC with split TDC in 28 nm CMOS

In this paper, an 800 MS/s 12bit voltage-time hybrid domain ADC is presented. A four-channel split time-to-digital converter (TDC) is proposed in the first-stage sub-TDC, effectively reducing the impact of skew error. A configurable time amplifier (TA) is proposed to pre-configure the discharge voltage, optimizing the conversation rate and power consumption. The hybrid domain ADC verified in a 28-nm CMOS process with a core area of 0.033 mm2, which achieves 65.66 dB SNDR and 72.16 dB SFDR while consuming 7.93 mW from a single 0.9-V supply, resulting in Walden figure-of-merit (FoM) values of 6.34 fJ/conversion-step.

A Power-Efficient 16-bit 1-MS/s Successive Approximation Register Analog-to-Digital Converter with Digital Calibration in 0.18 μm Complementary Metal Oxide Semiconductor

A power-efficient 16-bit 1-MS/s successive approximation register (SAR) analog-to-digital converter (ADC) is presented in this paper. High-bit sampling makes the bridge capacitance in the digital-to-analog converter (DAC) a unit one, eliminating fractional capacitance mismatch. The high-precision comparator is composed of a four-stage preamplifier and a strong-arm latch, with auto-zeroing used to mitigate input offset further. Digital foreground calibration based on low-bit weight is implemented to correct DAC capacitance mismatch. The post-layout simulation results show that the core ADC achieves 95.61 dB SNDR and 105.1 dB SFDR with calibration, consuming 5.4 mW power under a 3.3 V supply voltage, corresponding to a Schreier figure of merit (FoM) of 175.3 dB. The ADC core area is 1.06 mm2 in the 180 nm CMOS technology.

A 9-10-Bit Adjustable and Energy-Efficient Switching Scheme for Successive Approximation Register Analog-to-Digital Converter with One Least Significant Bit Common-Mode Voltage Variation.

A 9-10-bit adjustable and energy-efficient switching scheme for SAR ADC with one-LSB common-mode voltage variation is proposed. Based on capacitor-splitting technology and common-mode conversion techniques, the proposed switching scheme reduces the DAC switching energy by 96.41% compared to the conventional scheme. The low complexity and the one-LSB common-mode voltage offset of this scheme benefit from the simultaneous switching of the reference voltages of the capacitors corresponding to the positive array and the negative array throughout the entire reference voltage switching process, and the reference voltage of each capacitor in the scheme does not change more than two voltages. The post-layout result shows that the ADC achieves the 54.96 dB SNDR, the 61.73 dB SFDR, and the 0.67 μw power consumption with the 10-bit mode and the 48.33 dB SNDR, the 54.17 dB SFDR, and the 0.47 μw power consumption with the 9-bit mode in a 180 nm process with a 100 kS/s sampling frequency.

A Sub-1μW 16-Bit Fully Dynamic Zoom ADC Compatible With Free-Running and Incremental Modes Using Residue Feedforward and Extended Counting Techniques

This paper proposes a fully dynamic zoom ADC, which uses the residue feedforward technique to reduce the “fuzz” caused by the coarse SAR ADC’s quantization noise leakage in free running mode, and uses the extended counting technique to obtain the quantization error in incremental mode. The zoom ADC achieves high resolution in both modes. An improved cascoded floating-inverter-amplifier based integrator is used for low power and fully dynamic conversion. Fabricated in a standard 180nm CMOS process, the zoom ADC occupies an active area of 0.204mm, and consumes less than 1μW while achieving 102.1dB and 97.6dB SNDR in 95Hz bandwidth (BW) in free-running and incremental modes, respectively, corresponding to 182.2dB and 177.5dB FoMSNDR.

A Hybrid Energy-Efficient, Area-Efficient, Low-Complexity Switching Scheme in SAR ADC for Biosensor Applications.

A hybrid energy-efficient, area-efficient, low-complexity switching scheme in SAR ADC for biosensor applications is proposed. This scheme is a combination of the monotonic technique, the MSB capacitor-splitting technique, and a new switching method. The MSB capacitor-splitting technique, as well as the reference voltage Vaq allow for more options for reference voltage conversion, resulting in higher area savings and higher energy efficiency. In a capacitor array, the circuit performs unilateral switching during all comparisons except for the second and last two comparisons, reducing the difficulty in designing the drive circuit. The proposed switching scheme saves 98.4% of the switching energy and reduces the number of unit capacitors by 87.5% compared to a conventional scheme. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low-sampling error-sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrated that the proposed SAR ADC achieves 61.51 dB SNDR, 79.21 dB SFDR and consumes 0.278 μW of power in a 180 nm process with a 1 V power supply, a full swing input signal frequency of 23.33 kHz, and a sampling rate of 100 kS/s.

A 10-kHz BW 104.3-dB DR discrete-time delta-sigma modulator with ring-amplifier-based integrator

This paper presents a 3rd-order discrete-time delta-sigma modulator (DT DSM) with ring-amplifier-based integrators. To fulfill the performance requirement of the switched-capacitor (SC) integrator for the DSM with low power consumption, a dynamic ring amplifier is employed to replace the conventional continuous-time operation transconductance amplifier (OTA) in the integrator. The offset and 1/f noise of the 1st-stage integrator are further suppressed with an auto-zero structure. The quantizer is realized by a 3-bit flash analog-to-digital converter (ADC) to reduce the quantization noise power, while the mismatch in the feedback digital-to-analog converter (DAC) is suppressed by a dynamic weighting averaging (DWA) circuit. The DT DSM prototype is fabricated with a 0.18-μm CMOS process with an active area of 1.39 mm2, achieving 99.3 dB SNDR and 104.3 dB DR with a signal bandwidth of 10 kHz and an oversampling ratio of 128. The power consumption is 963.9 μW under a 3.3V power supply, corresponding to a Schreier figure-of-merit(FoMs) value of 174.5 dB.

A Low-Power SAR ADC with Capacitor-Splitting Energy-Efficient Switching Scheme for Wearable Biosensor Applications.

A low-power SAR ADC with capacitor-splitting energy-efficient switching scheme is proposed for wearable biosensor applications. Based on capacitor-splitting, additional reference voltage Vcm, and common-mode techniques, the proposed switching scheme achieves 93.76% less switching energy compared to the conventional scheme with common-mode voltage shift in one LSB. With the switching scheme, the proposed SAR ADC can lower the dependency on the accuracy of Vcm and the complexity of digital control logic and DAC driver circuits. Furthermore, the SAR ADC employs low-noise and low-power dynamic comparators utilizing multi-clock control, low sampling error sampling switches based on the bootstrap technique, and dynamic SAR logic. The simulation results demonstrate that the ADC achieves a 61.77 dB SNDR and a 78.06 dB SFDR and consumes 4.45 μW of power in a 180 nm process with a 1 V power supply, a full-swing input signal frequency of 93.33 kHz, and a sampling rate of 200 kS/s.

A 1.8 V 115.52 dB Third-Order Discrete-Time Sigma-Delta Modulator Using Nested Chopper Technology

A Sigma-Delta modulator (SDM) realized with a fully differential third-order single-loop cascaded integrator feedforward (CIFF) architecture is proposed. A pair of low-frequency chopper switches are nested outside the chopper amplifier to further reduce the residual offset voltage. To reduce the power consumption and ensure linearity, a high-speed dynamic comparator is also used to implement a one-bit quantizer. The proposed architecture and the corresponding functionality are first simulated in MATLAB Simulink at the behavioral level. The results show that the designed modulator has an SNDR of 124.9[Formula: see text]dB corresponding to an ENOB of 20.46 bits at a clock frequency of 256[Formula: see text]kHz and 312.5[Formula: see text]Hz input with a differential-mode voltage of 700[Formula: see text]mV sinusoidal waveform. Based on SMIC 180[Formula: see text]nm/1.8[Formula: see text]V standard CMOS process on the Cadence platform, the subcircuit-level simulation is also performed, while the result shows that the proposed modulator can effectively achieve 115.52[Formula: see text]dB SNDR, 18.90-bit ENOB, and 8.40[Formula: see text]mW power consumption, which correspond to FoM[Formula: see text] and FoM[Formula: see text] of 0.067[Formula: see text]pJ/step and 163.27[Formula: see text]dB, respectively. The proposed modulator shows a significant advantage to be applied for high-precision analog-to-digital conversion applications such as high-quality equipment for audio, ECG and EEG signal sensing.

A 600 MHz-BW 154.3 dB-FoM current-mode continuous-time pipelined ADC in 12 nm CMOS

A current-mode two-stage continuous-time pipelined (CTP) ADC for wideband receivers is proposed in this paper, to eliminate power-hungry front-end trans-impedance amplifier (TIA). An improved current mirror with low input impedance and high linearity is used to receive the current input signal and duplicate it to the delay chain and the quantization path of the 3-bit first stage. Then, the residue current is amplified and filtered by an embedded 1st-order TIA and further quantized by the second stage, which is implemented by a VCO-based quantizer to improve ADC energy efficiency and anti-aliasing filtering. Simulation results in a 12 nm FinFET process show that clocked at 4.8 GS/s, the proposed ADC achieves 55.7 dB SNDR for a 600 MHz bandwidth and consumes only 83.4 mW power under supplies of 0.9 V, 1.2 V, and 1.5 V, corresponding to an excellent FoM of 154.3 dB.

A 79.2-μW 19.5-kHz-BW 94.8-dB-SNDR Fully Dynamic DT ΔΣ ADC Using CLS-Assisted FIA With Sampling Noise Cancellation

This brief proposes a fully dynamic discrete-time (DT) Σ ADC using a correlated level shifting (CLS)-assisted floating inverter amplifier (FIA) with a sampling noise cancellation (SNC) technique. The CLS-assisted FIA improves amplifier gain with a single-stage configuration, which has lower input-referred noise than the cascaded one. In combination with the proposed SNC, the noise contribution of the 1st-stage integrator can be minimized. We also propose a novel passive integrator cascaded with a passive adder that avoids unwanted inter-stage loading without a speed penalty. The prototype of the proposed ADC fabricated in a 65 nm bulk CMOS process realizes a fully dynamic operation and achieves 94.8 dB SNDR with an OSR of 256 for 19.5 kHz bandwidth while consuming 79.2 W from a 1.2V supply at a 10 MHz sampling frequency. The Schreier and Walden FoMs are respectively 178.7 dB and 45.2 fJ/conv.-step, which are the best among recent fully dynamic DT Σ ADCs with similar bandwidth.

Fully Dynamic Zoom-ADC Based on Improved Swing-Enhanced FIAs Using CLS Technique With 1250× Bandwidth/Power Scalability

This brief proposes a fully dynamic zoom ADC based on improved swing-enhanced floating-inverter amplifiers (SEFIAs) using the correlated-level-shifting (CLS) technique with 1250× bandwidth/power scalability, by only changing the clock frequency. The improved SEFIA with CLS uses a reused capacitor to replace the dynamic biasing capacitor and input coupling capacitor, which simultaneously achieves both high gain and high output swing. Fabricated in a 55nm CMOS process, the prototype ADC with near-constant energy efficiency, which scales power from 453nW to 122μW, achieves high resolution (> 95.2 dB) and high DR (> 96.7 dB) during the scalable bandwidth. At 5kHz BW, it achieves 97.3dB DR, 96.3dB SNDR, and 112.2dB SFDR, leading to FoMDR of 177.1dB and FoMSNDR of 176.1dB.

A 24-kHz BW 90.5-dB SNDR 96-dB DR continuous-time delta-sigma modulator using FIR DAC feedback

This paper presents a single bit continuous time delta-sigma modulator (CTDSM) with finite impulse response (FIR) feedback DAC designed for audio applications. By using FIR feedback in the input stage, the linearity requirements of the first integrator are relaxed, and the clock jitter sensitivity is reduced, as seen in a multi-bit quantizers. The choppers, working in conjunction with the FIR DAC, effectively suppresses in-band aliasing noise generated by the chopper in the first integrator. A fast comparator serves as a single-bit quantizer, and the 9.2% TS loop delay eliminates the need for excess loop delay compensation in the modulator. Energy efficient integrators are implemented using the current-starved OTA. The CTDSM prototype was fabricated using a 180-nm CMOS process, achieving a 90.5 dB SNDR and 96 dB DR with a 24 kHz signal bandwidth. The power consumption is 210 μ W, corresponding to a Schreier figure-of-merit value of 171.1 dB.

A 14-Bit Oversampled SAR ADC With Mismatch Error Shaping and Analog Range Compensation

DAC mismatch is a major challenge for high-resolution ADCs. This paper proposes an analog-detection-based input range compensation technique for high-resolution ADCs with mismatch error shaping (MES). By applying a pre-comparison and suitably switching the DAC MSB, the input loss caused by MES is compensated. By adopting a flying-capacitor sampling technique, the prediction errors found in prior solutions are avoided. The prototype 14-bit SAR ADC achieves 80.4 dB SNDR and 93 dB SFDR in a 4 kHz signal bandwidth with an OSR of 16. It only occupies 0.0034 mm and consumes 0.656 μW under a 0.8 V supply, leading to a Schreier figure-of-merit of 178.3 dB. These features make it suitable for miniaturized high-performance IoT and biomedical systems.

Behavioral Modeling and Circuit Design of High Precision Low Power Dynamic Zoom ADC

In this paper, a high-precision, energy-saving dynamic zoom ADC consisting of a 6-bit SAR ADC and a second-level Σ − ∆ modulator (SDM) is proposed. Non-ideal factors, including slew rate (SR), limited bandwidth and DC gain of the op-amp, and kT/C noise, mismatch of DAC capacitors, are analyzed with a behavioral model in Simulink to guide actual circuit design more accurately. The ADC parameters are adjusted and optimized by model simulation. Because the DAC capacitors mismatch produces harmonic distortion, the DWA technique is used. A new digital combined circuit is proposed to minimize power consumption. To further improve its energy efficiency, a gain enhancement current mirror OTA is designed and the SAR ADC adopts upper plate sampling technique. The layout of zoom ADC occupies 0.856 mm2 in 65 nm techniques. It achieves 109.2 dB SNDR, 17.84 bits ENOB at 1 kHz signal bandwidth and consumes only 0.233 mW.

A Σ-Δ Modulator Based on an Inverter-based Integrator with Dynamic Current Switch

This paper presents a low-power high-resolution 3rd-order 1-bit Σ-Δ modulator based on an inverter-based integrator with a dynamic current switch. To reduce the power consumption of the modulator circuit, a dynamic current switch branch is added to form a low-power inverter-based integrator. A 3rd-order 1-bit Σ-Δ modulator is designed in a TSMC 65 nm CMOS technology to verify the effectiveness of the proposed integrator circuit. The prototype Σ-Δ modulator achieves 102.4 dB SNDR, 16.71 Bit ENOB in a 2 KHz signal BW at an Over Sampling Ratio (OSR) of 160, while consuming only 29.5-μW. And the FOMSNDR is 180.7 dB.

Complete design approach of a 3rd order continuous-time sigma-delta ADC with FIR feedback and low-noise low-distortion op-amp achieving 101.8 dB SNDR and −110dB THD

This paper presents a step-by-step design approach of a 3rd order continuous-time sigma-delta modulator with a 4-tap FIR feedback DAC achieving 107 dB DR (A-weighted), −110 dB THD and an SNDR of 101.8 dB. The THD is achieved through a fully differential feed-forward compensated op-amp that maintains high linearity with the aid of a class AB output stage and an optimum bias current through a CMFB loop. The modulator consumes 322.5uW of power while taking an area of 0.2925 mm2.

A Wide Dynamic Range Sigma-Delta Modulator for EEG Acquisition Using Randomized DWA and Dynamic-Modulated Scaling-Down Techniques

This paper proposes a wide dynamic range (DR) and high-resolution discrete-time (DT) 2-order 4-bit sigma-delta modulator with a novel dynamic-modulated scaling-down (DM-SD) technology for non-invasive electroencephalogram (EEG) acquisition. The DM-SD technology can expand the input dynamic range and suppress large input offsets at the same time. The modulator was designed with 180nm CMOS technology with an area of 0.49 mm2. We achieve a 118.1 dB SNDR when the input signal is 437.5 Hz and the signal bandwidth is 1500 Hz. Due to the proposed DM-SD technology, the DR is expanded to 126 dB. The power consumption of the whole modulator is 1.6 mW and a 177.8 dB Schreier figure-of-merit (FoMs) is realized.