dB Noise Figure Research Articles

A fully integrated direct-conversion digital satellite tuner in 0.18 μm CMOS

A fully integrated direct-conversion digital satellite tuner for DVB-S/S2 and ABS-S applications is presented. A broadband noise-canceling Balun-LNA and passive quadrature mixers provided a high-linearity low noise RF front-end, while the synthesizer integrated the loop filter to reduce the solution cost and system debug time. Fabricated in 0.18 μm CMOS, the chip achieves a less than 7.6 dB noise figure over a 900–2150 MHz L-band, while the measured sensitivity for 4.42 MS/s QPSK-3/4 mode is −91 dBm at the PCB connector. The fully integrated integer-N synthesizer operating from 2150 to 4350 MHz achieves less than 1 °C integrated phase error. The chip consumes about 145 mA at a 3.3 V supply with internal integrated LDOs.

An Optimum Body Biasing for Gain and Linearity Control in CMOS Low-Noise Amplifiers

In this paper, an optimum body biasing for gain and linearity control in CMOS Low Noise Amplifier (LNA) is discussed. A digitally controlled highly linear CMOS LNA has been designed and implemented in a 0.13 μm CMOS process. An off chip Digital to Analog Converter (DAC) is used to generate the proper body bias voltage corresponding to a maximum of the input referred third order intercept point (IIP3). The LNA is suitable for reconfigurable purposes due to its smooth control of gain and linearity. It is dedicated to wireless sensor network applications in the 2.4 GHz ISM Band. The circuit achieves 12.4 dB nominal gain, 4.2 dB noise figure (NF), and ―1 dBm IIP3 while drawing 3.1 mA at a 1 V supply. When adjusting the body bias to ―0.55 V, the IIP3 peaks at 6 dBm for a 1.7 mA current consumption. The gain and NF are 8.9 dB and 6.2 dB respectively.

CMOS Direct-conversion Radio Transceiver Design for 5-GHz WLAN Applications

Direct-conversion radio transceiver chipsets for 5-GHz WLAN have been implemented in 0.18-/jm CMOS technology. The receiver front-end includes low flicker noise down-conversion mixers where the parasitic tail capacitances in the transconductance stage are resonated out at the operating frequency. To reduce the local oscillator pulling and leakage, an offset clock generator is implemented in which a voltage controlled oscillator operates at two-thirds of the operating frequency band. The transmitter front-end can drive up to 2 dBm output power at the driver amplifier. The receiver front-end has 6.5 dB noise figure, -13 dBm input IP3, and voltage gain of 20 dB. The overall receiver has voltage gain of 60 dB. The phase noise of the clock generator at 5 GHz frequency is -109 dBc/Hz at 1 MHz offset.

An X- and Ku-Band Wideband Recursive Receiver MMIC With Gain-Reuse

This paper presents an 8-18 GHz wideband receiver with recursive super-heterodyne topology. A multi-feedback technology is utilized in the LNA design for the input matching over the wide frequency range in X- and Ku-band. In order to save power, both the RF and IF signals share a tunable transconductance stage. The IF output of the first mixer is fed back into the tunable input stage for IF amplification in a recursive manner, which significantly enhances the gain tuning without increasing the power. The wideband receiver MMIC is implemented in a 0.13 SiGe BiCMOS technology and achieves a 6.7-7.8 dB noise figure. The receiver average gain over the frequency range is measured as 53 dB maximum gain with 20 dB continual tuning and 36 dB discrete tuning. The average output P1dB over the frequency range is measured as 10 dBm at maximum gain. The receiver dissipates only 180 mW with a 2.2 V power supply.

Noise performance of a frequency nondegenerate phase-sensitive amplifier with unequalized inputs

For the first time to our knowledge, the noise performance of a frequency nondegenerate phase-sensitive amplifier (PSA) with unequalized input powers has been experimentally characterized, based on a fiber-based parametric copier-PSA scheme. Two different noise-figure (NF) definitions-separate and combined NFs-are provided and compared. The results show that the separate NF of the weaker input wave is lower than that of the stronger wave due to the correlated-light nature. When considering the combined NF, the optimal noise performance (0 dB NF) is obtained only when the input powers are equal. Experiments agree well with the theoretical predictions.

High gain double-pass L-band EDFA with dispersion compensation as feedback loop

We demonstrate an efficient double-pass L-band erbium-doped fiber amplifier (EDFA) incorporating chirped fiber Bragg grating (CFBG). The amplifier structure exploits the characteristics of CFBG to reflect the amplified signal back into the gain medium, filter out the recycled forward amplified spontaneous emission and block the residual 1480 nm pump power. The amplifier configuration has high gain and low noise figures as compared to double-pass EDFA using broadband mirror. The demonstrated amplifier has gain of more than 48 dB and low noise figure of less than 4 dB at low input signal power of −40 dBm.

A Wideband Noise Cancelling Low Noise Amplifier for 3GPP LTE Standard

This paper presents the design of a wideband low noise amplifier (LNA) for the 3GPP LTE (3rd Generation Partnership Project Long Term Evolution) standard. The proposed LNA uses a common gate topology with a noise cancellation technique for wideband (0.7 to 2.7GHz) and low noise operation. The capacitive cross coupling technique is adopted for the common gate amplifier. Consequently input matching is achieved with lower transconductance, thereby reducing the power consumption and noise contribution. The LNA is designed in a 0.18µm process and the simulations show lower than -10dB input return loss (S11), and 2.4∼2.6dB noise figure (NF) over the entire operating band (0.7∼2.7GHz) while drawing 9mA from a 1.8V supply.

65 nm CMOS receiver with 4.2 dB NF and 66 dB gain for 60 GHz applications

A direct conversion receiver for 60 GHz applications is fabricated in 65 nm CMOS. It consists of three low-noise amplifier gain stages, an RF mixer, a lowpass filter and a three-stage programmable gain amplifier. An overall minimum noise figure (NF) of 4.2 dB and maximum gain of 66 dB is achieved by the receiver occupying a core area of 0.26 mm2 while drawing 36 mA of current from a 1 V supply.

능동 배열 레이더 시스템 구현을 위한 반도체형 송수신기 설계

This paper presents design and measurement result of S-band, kW solid-state transmitter and receiver for active array radar system. Transmitter characteristics show 63 dB gain, 200 usec pulse width(max.), 10 % duty(max.) and 63 dB pulse to pulse stability. Receiver characteristics show 23 dB gain and 3.2 dB noise figure. Receiving mode for pulse network analyzer is used for pulse to pulse stability measurement. Measurement results satisfies all specification.

A 25-GHz Compact Low-Power Phased-Array Receiver With Continuous Beam Steering in CMOS Technology

A compact low-power phased array receiver with continuous beam steering is presented based on the subsector beam steering technique. The entire beam steering range is divided into five subsectors from four characteristic beams of the Butler matrix. In each subsector the receive beam is steered by weighted combination of the received signals from array antennas. The theory of beam steering is detailed and the relationship of the steered angle with the beam steering factors is derived. The proposed architecture has lower circuit complexity and less power consumption because no challenging CMOS 360° variable phase shifters and multi-phase voltage-controlled oscillators are required. The phased array MMIC implemented in 0.13 μm CMOS technology has 17-21 dB receiving gain and 8.9-10.7 dB noise figure in 25-26 GHz. It consumes lower than 30 mW and takes a small chip area of 1.43 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The continuous beam steering is demonstrated over the spatial range from -90° to +90°.

3.7 mW 24 GHz LNA with 10.1 dB gain and 4.5 dB NF in 0.18 µm CMOS technology

A low-power 24 GHz low-noise amplifier (LNA) with flat and low noise figure (NF) using standard 0.18 µm CMOS technology is demonstrated. The low-power LNA consists of three cascaded common-source stages biased in the weak inversion region. To achieve sufficient gain, a series peaking inductor (LG3) was added to the input terminal of the third stage to boost the gain (simulation shows a 78.9% improvement (from 5.7 to 10.2 dB) at 24 GHz). Flat and low NF was achieved by adopting a slightly under-damped Q-factor for the second-order NF frequency response. Shunt RC feedback in conjunction with a low-Q RL load were adopted in the third stage to achieve excellent output impedance matching. The 24 GHz LNA achieved S21 of 10.1 dB and NF of 4.5 dB with a power dissipation (PDC) of only 3.7 mW, the lowest PDC ever reported for a 24 GHz-band CMOS LNA with S21 greater than 10 dB.

Systematic Width Determination for the Design of Power-Constrained Noise Optimization Inductively Degenerated Low Noise Amplifier

Systematic width determination for the inductively degenerated low noise amplifier (IDLNA) was implemented using power-constrained noise optimization (PCNO) technique. Using drain current for short channel equation, the power dissipated (PD) as a function of gate overdrive (VOV) expression was derived. This expression was further arranged to represent PD as a function of input stage quality factor (QS). The two relations were translated into contours which were generated at fixed noise figure (NF). By means of manipulating the same equations, the NF as a function of QS was derived. The contours were generated using the parameters specified for Silterra’s 0.18 μm CMOS process for Wideband-Code Division Multiple Access (W-CDMA) application. The PD versus VOV contours show that the NF of the LNA can be improved if PDis increased. These contours also illustrate that for a W-CDMA with a requirement of below 2.5 dB of NF, the VOVis in the range of 46–115 mV. The PD and NF versus QS contours show that minimum PD for each NF and minimum NF at each PD is maintained at QS equal to 4, independent of the process and operating frequency. This result is verified by derivations and comparisons with a referenced article. With the optimum QS known, the calculated transistor’s width is 330 μm to provide an NF of 1 dB at 6 mW of power.

A Low-Voltage Low-Power K-Band CMOS LNA Using DC-Current-Path Split Technology

A low-voltage low-power K-band low-noise amplifier (LNA) using 0.18 μm CMOS technology is presented in this letter. By splitting the dc current paths, the supply voltage of the LNA is effectively reduced. Moreover, the forward-biased body is adopted for the LNA to boost the gain. Furthermore, the high-value resistors are utilized between nMOS bodies and forward-body biases (V <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">B</sub> ) to prevent the signal leakage and noise coupling. The proposed LNA achieved a 13.2 dB gain and 4.1 dB noise figure at 20.5 GHz. The supply voltage and total dc power consumption are 0.6 V and 7.1 mW, respectively. To the author's knowledge, this LNA demonstrates the lowest supply voltage among previously published K-band 0.18 μm CMOS LNA.

A 60 GHz Phase Shifter Integrated With LNA and PA in 65 nm CMOS for Phased Array Systems

This paper presents the design of a 60 GHz phase shifter integrated with a low-noise amplifier (LNA) and power amplifier (PA) in a 65 nm CMOS technology for phased array systems. The 4-bit digitally controlled RF phase shifter is based on programmable weighted combinations of I/Q paths using digitally controlled variable gain amplifiers (VGAs). With the combination of an LNA, a phase shifter and part of a combiner, each receiver path achieves 7.2 dB noise figure, a 360° phase shift range in steps of approximately 22.5°, an average insertion gain of 12 dB at 61 GHz, a 3 dB-bandwidth of 5.5 GHz and dissipates 78 mW. Consisting of a phase shifter and a PA, one transmitter path achieves a maximum output power of higher than +8.3 dBm, a 360° phase shift range in 22.5° steps, an average insertion gain of 7.7 dB at 62 GHz, a 3 dB-bandwidth of 6.5 GHz and dissipates 168 mW.

A Subharmonic Receiver in SiGe Technology for 122$~$GHz Sensor Applications

The iterative design of an integrated subharmonic receiver for 120-127 GHz is presented. The receiver consists of a single-ended low-noise amplifier (LNA), a push-push voltage-controlled oscillator (VCO) with 1/32 divider, a polyphase filter, and a subharmonic mixer. The receiver is fabricated in SiGe:C BiCMOS technology with <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">fT</i> / <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">f</i> <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">max</sub> of 255 GHz/315 GHz. In the first design the differential down-conversion gain of the receiver is 25 dB at 127 GHz, and the corresponding noise figure (NF) is 11 dB. The 3 dB bandwidth reaches from 125 GHz to 129 GHz. The input 1 dB compression point is at - 40 dBm. The receiver draws 139 mA from a supply voltage of 3.3 V. A subsequent design demonstrates 31 dB differential gain at 122 GHz, and 11 dB NF. The 3 dB bandwidth is from 121 GHz to 124 GHz. The receiver has a NF of 8 dB for 3 GHz IF frequency due to integrated RF bandpass-filtering. It is realized by the lower NF of the LNA, and the LNA itself.

A 7‐ to 14‐GHz GaAs pHEMT LNA with 1.1 dB noise figure and 26 dB gain

AbstractA three‐stage 7‐ to 14‐GHz monolithic low‐noise amplifier (LNA) has been fabricated using 0.15‐μm AlGaAs/GaAs pHEMT technology.To achieve ultra low noise figure and wide operation bandwidth, the proposed LNA uses wideband matching network and negative feedback technique. Measured results from 7 to 14 GHz demonstrate a minimum of 1.1 dB noise figure and 26 dB gain. The input and output return loss exceeded 10 dB across the band. These results demonstrate the best performance of AlGaAs/GaAs pHEMT technology for wideband and low noise applications. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52:2615–2617, 2010; View this article online at wileyonlinelibrary.com. DOI 10.1002/mop.25547

An 18.85 mW 20–29 GHz wideband CMOS low‐noise amplifier with 3.85 ± 0.25 dB noise figure and 18.1 ± 1.9 dB gain

AbstractA 20–29 GHz wideband CMOS low‐noise amplifier (LNA) with flat and low noise figure (NF), flat and high‐gain (S21), and excellent phase linearity property (group‐delay‐variation is only ±22.6 ps across the whole band) is demonstrated.To achieve flat and low NF, the size, layout, and bias of the input transistor were first optimized for minimum NF, and then the inductance of the input inductors was tuned to obtain a slightly under‐damped (flat) NF frequency response. In addition, to achieve flat and high S21 and small group‐delay‐variation, the inductive‐peaking technique was adopted in the current‐reused stage for bandwidth enhancement. The LNA consumed 18.85 mW power and achieved flat and low NF of 3.85 ± 0.25 dB, and flat and high S21 of 18.1 ± 1.9 dB over the 20–29 GHz band of interest. These are the best NF and S21 performances ever reported for a 21.65–26.65 GHz or a 22–29 GHz wideband CMOS LNA. © 2010 Wiley Periodicals, Inc. Microwave Opt Technol Lett 52: 2017–2020, 2010; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.25380

Complementary UWB LNA Design Using Asymmetrical Inductive Source Degeneration

This letter proposes a novel LNA design method where the complementary transistor topology is combined with asymmetrical inductive source degeneration to achieve matched input impedance over a wide bandwidth. A 2-10 GHz LNA is designed and fabricated using a commercial 0.18 RF-CMOS process to verify the feasibility of our proposed method. In the intended bandwidth, this LNA has matched input impedance, 20 dB power gain, and 2.4-3.4 dB noise figure, with 25.65 mW power consumption.

A low-power 3.1–10.6 GHz ultra-wideband CMOS low-noise amplifier with common-gate input stage

A low-power ultra-wideband (UWB) low-noise amplifier (LNA) is proposed exploiting a current-reused technique operating in the frequency range of 3.1–10.6 GHz. The technique stacks two-stage amplifiers in dc, thereby reusing the dc current and saving the power consumption significantly. With the common-gate configuration at the input stage, broad-band input matching is obtained with less than −5 dB input reflection coefficient in 3–10 GHz frequency range. Fabricated with 0.18-μm RFCMOS technology, the proposed LNA achieves about 10 dB power gain and noise figure (NF) of 4.6–7.8 dB within 3 dB bandwidth of 2.2–9.7 GHz. The LNA core excluding the buffer consumes only 2.9 mW from a 1.8 V supply voltage. The input third order intercept point (IIP3) of the LNA is −8.5 dBm at 6 GHz.

Modeling and measurement of the noise figure of a cascaded non-degenerate phase-sensitive parametric amplifier

Semi-classical noise characteristics are derived for the cascade of a non-degenerate phase-insensitive (PI) and a phase-sensitive (PS) fiber optical parametric amplifier (FOPA). The analysis is proved to be consistent with the quantum theory under the large-photon number assumption. Based on this, we show that the noise figure (NF) of the PS-FOPA at the second stage can be obtained via relative-intensity-noise (RIN) subtraction method after averaging the signal and idler NFs. Negative signal and idler NFs are measured, and <2 dB NF at >16 dB PS gain is estimated when considering the combined signal and idler input, which is believed to be the lowest measured NF of a non-degenerate PS amplifier to this date. The limitation of the RIN subtraction method attributed to pump transferred noise and Raman phonon induced noise is also discussed.