CMOS Direct-conversion Radio Transceiver Design for 5-GHz WLAN Applications

Abstract

Direct-conversion radio transceiver chipsets for 5-GHz WLAN have been implemented in 0.18-/jm CMOS technology. The receiver front-end includes low flicker noise down-conversion mixers where the parasitic tail capacitances in the transconductance stage are resonated out at the operating frequency. To reduce the local oscillator pulling and leakage, an offset clock generator is implemented in which a voltage controlled oscillator operates at two-thirds of the operating frequency band. The transmitter front-end can drive up to 2 dBm output power at the driver amplifier. The receiver front-end has 6.5 dB noise figure, -13 dBm input IP3, and voltage gain of 20 dB. The overall receiver has voltage gain of 60 dB. The phase noise of the clock generator at 5 GHz frequency is -109 dBc/Hz at 1 MHz offset.