dB Double Side Band Research Articles

A Ka Band FMCW Transceiver Front-End With 2-GHz Bandwidth in 65-nm CMOS

A fully integrated Ka band frequency modulation continuous wave single-chip radar transceiver front-end is proposed in 65-nm CMOS technology. By utilizing VCO with multi-biasing varactor banks, the critical bandwidth and linearity have been improved. To address the challenges of losses and complexities in local oscillator (LO) distribution chain, a three-way transformer-based power divider is proposed and implemented to split the input differential signals to three outputs, in three orthogonal directions. The poly phase filter is also used to obtain the in-phase and quadrature LO signals. To minimize the reflections between the poly phase filter and the following stages, a 1:2 transformer is inserted to provide sufficient matching. For the receiver part, differential cascode amplifier with neutralization capacitors is implemented in the low noise amplifier to obtain gain and stability. By utilizing double balanced passive mixers, noise performances of I/Q paths are improved at low intermediate frequency. The transceiver demonstrates 4.4-dBm output power, 2-GHz bandwidth with 7.5-cm range resolution, and 5.9–7.5 dB double side band noise figure at 4 MHz. The whole transceiver front-end consumes 132 mW from 1.2 V and 2.16 mm2 die size.

A Monolithic Dual-Band 77/94 GHz Transceiver Front-End With Shared Frequency Multiplier

This paper presents a monolithic dual-band 77/94 GHz transceiver front-end with shared frequency multiplier. The transceiver front-end consists of two transmitters and receivers, operating at 77 GHz and 94 GHz respectively to support dual-band operation. In order to reduce the dc power consumption and save chip area, a shared frequency multiplier between the two bands is adopted in this work. We employ a frequency tripler cascaded with a doubler as the frequency multiplier to generate the desired 77 GHz signal and to lower down the frequency and phase noise of the local-oscillator (LO). The 94 GHz signal is produced by the generated 77 GHz signal up-mixing with the LO input to share the frequency multiplier for low power and low cost. The conversion gain of the multiplier is boosted by the efficiency enhancement technique in frequency tripler and the proposed gain boosting unit in the output power buffer. Besides, a frequency shunt network at the mixer output is utilized to short the unwanted mixed signal and improve the linearity of the 94 GHz transmitter. The measured saturated output power ${{P_{sat}}}$ and 3-dB bandwidth of the 77/94 GHz band transmitter are 14.2/12.35 dBm and 7.5/6 GHz, respectively. A 37.05/27.7 dB receiver conversion gain, 8.8/14.8 dB double side band noise figure are measured in the 77/94 GHz band receiver. The transceiver occupies a core area of 1.12 mm $\times2.46$ mm and draws 450 mA from a 1.2 V supply voltage.

Design techniques for mitigation of intermodulation distortion components in CMOS RF receiver front-end circuits with subthreshold operation

This paper provides an overview of target applications and design aspects for emerging radio frequency front-end circuits with subthreshold biasing to reduce power consumption. Design methods are described to linearize a subthreshold pseudo-differential common-source cascode low-noise amplifier (LNA) and a subthreshold active mixer. The linearization techniques can improve the third-order intermodulation intercept point (IIP3) through the use of passive components, which implies that they do not require auxiliary amplifiers to suppress third-order distortion components, and therefore do not incur any extra power consumption. A 1.95 GHz receiver front-end chip with a narrowband LNA and down-conversion mixer was designed and fabricated in 110 nm CMOS technology. Measurement results show that the linearized low-power front-end has a 20.6 dB voltage gain, a 9.5 dB double sideband noise figure, and a − 10.8 dBm IIP3 with a power consumption of 0.9 mW.

A Low-Power, High-Gain, and Low-Noise 802.11a Down-Conversion Mixer in 0.35-μm SiGe Bi-CMOS Technology

The paper presents a novel 5.15[Formula: see text]GHz–5.825[Formula: see text]GHz SiGe Bi-CMOS down-conversion mixer for WLAN 802.11a receiver. The architecture used is based on Gilbert cell mixer, the combination of MOS transistors and HBT BJT transistor device characteristics. The hetero-junction bipolar transistor (HBT) topology is adopted at the transconductance stage to improve power gain and reduce noise factor, and the LO series-parallel CMOS switch topology will be applied to reduce supply voltage and dc power at the switching stage. This mixer is implemented in TSMC 0.35-[Formula: see text]m SiGe Bi-CMOS process, and the chip size including the test pads is 1.175*0.843[Formula: see text]mm2. The main advantages for the proposed mixer are high conversion gain, a moderate linearity, low noise figure, and low power. The post-simulation results achieved are as follows: 14[Formula: see text]dB power conversion gain, [Formula: see text]6[Formula: see text]dBm input third-order intercept point (IIP3), 6.85[Formula: see text]dB double side band (DSB) noise figure. The total mixer current is about 1.54[Formula: see text]mA from 1.4[Formula: see text]V supply voltage including output buffer. The total dc power consumption is 2.15[Formula: see text]mW.

An RF front-end with an automatic gain control technique for a U/V band CMMB receiver

This paper presents a fully integrated RF front-end with an automatic gain control (AGC) scheme and a digitally controlled radio frequency varied gain amplifier (RFVGA) for a U/V band China Mobile Multimedia Broadcasting (CMMB) direct conversion receiver. The RFVGA provides a gain range of 50 dB with a 1.6 dB step. The adopted AGC strategy could improve immunity to adjacent channel signal, which is of importance for CMMB application. The front-end, composed of a low noise amplifier (LNA), an RFVGA, a mixer and AGC, achieves an input referred 3rd order intercept point (IIP3) of 4.9 dBm with the LNA in low gain mode and the RFVGA in medium gain mode, and a less than 4 dB double side band noise figure with both the LNA and the RFVGA in high gain mode. The proposed RF front-end is fabricated in a 0.35 μm SiGe BiCMOS technology and consumes 25.6 mA from a 3.0 V power supply.

A low-voltage ultra-wideband down-conversion mixer with improved power conversion gain

This article presents a wideband mixer using a TSMC 0.18 µm complementary metal-oxide semiconductor technology process for ultra-wideband (UWB) system applications. The measured 3-dB radio frequency (RF) bandwidth is from 3 to 8.4 GHz with an intermediate frequency of 10 MHz. The measurement results of the proposed mixer achieve 8.1 dB average power conversion gain −5 dBm input third-order intercept point (IIP3) at 7.4 GHz and 12.4–13.3 dB double side band noise figure. The total dc power consumption of this mixer including output buffers is 3.18 mW from a 1 V supply voltage. The output current buffer consumption is about 2.26 mW with an excellent local oscillator-RF isolation of up to 40 dB at 5 GHz. The article presents a mixer topology that is greatly suitable for low-power operation in UWB system applications.

A Resistively Degenerated Wideband Passive Mixer With Low Noise Figure and High ${\rm IIP}_{2}$

A CMOS mixer whose linearity is maintained for a wide frequency range is presented. Transconductance ( <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">Gm</i> ) boosting methods, such as input cross-coupling, current reuse complementary input, and back gate connection, are used to improve overall gain and noise performance. A source-degenerated passive mixer is used to improve noise figure (NF) by increasing the equivalent mixer output impedance. The operating frequency is from 1.55 to 2.3 GHz. The measured performance shows less than 9.5 dB double-sideband (DSB) NF, more than 22-dB voltage gain, better than +50 dBm uncalibrated IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> , and higher than +7 dBm of IIP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">3</sub> , while consuming only 10 mW from a 2-V supply. A 0.18-¿m Si CMOS process with metal-insulator-metal capacitors is used.

A Broadband Low-Cost Direct-Conversion Receiver Front-End in 90 nm CMOS

Transistors in aggressively scaled CMOS technologies have f <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">T</sub> greater than 150 GHz, which exceeds requirements for most existing commercial applications below 10 GHz. Excess transistor performance can be traded-off for cost by designing out inductors. This paper presents a prototype which exploits the speed of transistors to design highly integrated broadband receiver front-ends. The inductor-less prototype operates from 2 to 5.8 GHz and dissipates 85 mW at 5 GHz while occupying 0.2 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> active area. It provides 44 dB of gain, 3.4 dB double side band noise figure, 21 dBm in-band IIP3 in the highest gain mode and 15 dB input matching.

A 2-GHz Low-Power Down-Conversion Mixer in 0.18- m CMOS Technology

A low-voltage and low-power RF mixer for WCDMA applications is presented. The paper presents a novel topology mixer that leads to a better performance in terms of isolation and power consumption for low supply voltage. The measuring results of the proposed mixer achieve: 7dB power conversion gain, 10.4dB double side band (DSB) noise figure, -2dBm input third-order intercept point (IIP3), and the total dc power consumption of this mixer including output buffers is 2.2mW from a 1V supply voltage. The current output buffer is about 1.96mW, the excellent LO-RF, LO-IF and RF-IF isolation achieved up to 49dB, 39.5dB and 57.3dB, respectively.

Design of low-cost 183 GHz subharmonic mixers for commercial applications

Techniques are presented for designing fixed-tuned millimetre-wave components with the least number of parts to minimise the cost and maximise the potential for volume manufacture. Design techniques for millimeter-wave mixer components targeted at potentially high volume applications, such as medical and security screening and nondestructive testing, require certain compromises in the use of CAD tools. The compromise techniques are demonstrated using commercially available foundry diodes in the design of a 183 GHz subharmonic mixer for earth observation applications. The resulting mixer exhibits 6.85 dB double sideband conversion loss and a mixer temperature of 988 K using 5 mW of local oscillator power at 92 GHz.

Sixty-GHz-band ultra-miniature monolithic T/R modules for multimedia wireless communication systems

The development of 60 GHz-band ultra-miniature FM/frequency-shift keying (FM/FSK) transmitter/receiver modules fabricated with a complete monolithic-microwave integrated circuits (MMIC) chip set, including dielectrically stabilized fundamental-frequency oscillators for multimedia wireless communication systems, is reported. The 0.9 cc transmitter module, which consists of a voltage controlled oscillator (VCO) and two power amplifiers, exhibits 11.5 MHz/V modulation sensitivity, 10.2 dBm output power, and -2.4 ppm//spl deg/C frequency stability. With the receiver module, which consists of low noise amplifier (LNA), a mixer, and a local oscillator (LO), 5.4 dB double-side band (DSB) noise figure with 10.8 dB downconversion gain has been achieved. The 60 GHz band monolithic dielectric-resonator (DR) stabilized oscillators offer a practical approach to ultra miniature transmitter/receiver modules for high-speed wireless LAN systems with data rates greater than 10 Mbps and for video-signal and compressed HDTV-signal (MUSE) transmission systems.

Practical low-noise quasiparticle receiver for 80–100 GHz

We have tested a heterodyne receiver for millimetre-wave radio astronomy, which uses a quasiparticle mixer with junctions of Pb/Bi/In-oxide-Pb/Bi. A receiver noise temperature of around 100 K double sideband has been measured with a number of different junctions. For one junction, the best receiver temperature obtained was 73 K, and the mixer conversion loss was less than 5.8 dB double sideband.

Airborne Imaging System Using a Cryogenic 90-Ghz Receiver

A cryogenic 90-GHz receiver has heen developed with a noise figure of 2.36 dB ((double sideband) (DSB)) and an instantaneous band-width of 1.2 GHz. The cooled front-end consists of a Schottky-barrier mixer followed by a GaAs FET IF amplifier. The radiometer is small in size and weighs only 52 kg, including the refrigerator system. It is part of an airborne imaging system, that has been fight-tested aboard a Dornier Do 28 aircraft. First test results are presented.