Data Recovery Circuit Research Articles

A 0.5-to-2.5 Gb/s Reference-Less Half-Rate Digital CDR With Unlimited Frequency Acquisition Range and Improved Input Duty-Cycle Error Tolerance

Clock and data recovery (CDR) circuits with wide frequency acquisition range offer flexibility in optical communication networks, help reduce link power through activity-based rate adaptation, and minimize cost with a single-chip multi-standard solution. Extracting the bit rate from the incoming random data stream is the main challenge in implementing reference-less CDRs. A conventional rotational frequency detector has a limited acquisition range of about ±50% of the VCO frequency, consumes large power, and is susceptible to harmonic locking. Extending its range requires additional high-speed circuitry and a complex state machine [1]. The DLL-based architecture in [2] requires passing high-speed data through a long string of power-hungry buffers, imposes stringent matching requirements, and works only with ring oscillators. Other approaches require detailed statistical [3] or timing analysis [4]. Further, all the above techniques are only suitable for full-rate CDRs. In this paper, we present a reference-less half-rate CDR that uses a sub-harmonic extraction method to achieve unlimited frequency acquisition range. This technique is capable of locking the CDR to within 40ppm of any sub-rate of the data (making it applicable for any sub-rate CDR architecture), while being immune to undesirable harmonic locking. This CDR also integrates a calibration loop to improve robustness to input duty cycle error.

Dynamic Sleep-Mode ONU With Self-Sustained Fast-Lock CDR IC for Burst-Mode Power Saving in 10 G-EPON Systems

A novel power saving optical network unit (ONU) employing a self-sustained fast-lock clock and data recovery (CDR) circuit IC for 10 Gigabit Ethernet passive optical network (10 G-EPON) is presented. With its self-generated quasi-synchronized signal-based bursty CDR control, a fast wake-up time of the ONU within 497 ns supporting heavy-duty dynamic bandwidth allocation (DBA) cycles is fully achieved. A high power consumption reduction efficiency of 63.8%, compared to the typical Doze-mode power saving ONU, was also realized.

An ASIC Design of a High-Speed Clock and Data Recovery Circuit

Clock and Data Recovery (CDR) means that the digital data streams are sent without an accompanying clock signal. A digital CDR circuit is proposed as it does not depend on the special analog process and provide higher immunity to the noise. This design is fabricated using 0.13μm standard process and the circuit can support up to 5 GHz data rate to support the high speed standard. Compared to other CDR design with more advanced technology, our implementation can have similar performance but the manufacturing cost can be reduced.

A CMOS 5.4/3.24-Gbps Dual-Rate CDR with Enhanced Quarter-Rate Linear Phase Detector

This paper presents a clock and data recovery circuit that supports dual data rates of 5.4 Gbps and 3.24 Gbps for DisplayPort v1.2 sink device. A quarter-rate linear phase detector (PD) is used in order to mitigate high speed circuit design effort. The proposed linear PD results in better jitter performance by increasing up and down pulse widths of the PD and removes dead-zone problem of charge pump circuit. A voltage-controlled oscillator is designed with a ‘Mode’ switching control for frequency selection. The measured RMS jitter of recovered clock signal is 2.92 ps, and the peak-to-peak jitter is 24.89 ps under 2 31 –1 bit-long pseudo-random bit sequence at the bitrate of 5.4 Gbps. The chip area is 1.0 mm×1.3 mm, and the power consumption is 117 mW from a 1.8 V supply using 0.18 µm CMOS process.

A wide range, low power clock and data recovery scheme for RFID tags

An extremely low power clock and data recovery (CDR) circuit that covers a large input speed range is reported in this paper. The CDR recovers accurately-synchronized clock and data directly from the pulse position modulated (PPM) input, and the bit information embedded in time domain is converted into a voltage through charging integration on linear capacitors. The threshold voltage required for data recovery is accurately generated from the input bit period to produce the best noise margin for both bit 1 and bit 0. Furthermore, the current that is used for charge integration is dynamically set by a feedback loop to expand the input speed range. The prototype CDR circuit was implemented using a standard CMOS 0.25 μm technology. Results show that the designed prototype can cover a large input speed range from 0.5 to 500 kbit/s, while only consumes 11---75 μW of power, respectively.

A 1–16-Gb/s Wide-Range Clock/Data Recovery Circuit With a Bidirectional Frequency Detector

A 1-16-Gb/s wide-range clock and data recovery (CDR) circuit is presented by using the proposed bidirectional frequency detector. This CDR circuit is fabricated in 0.13-μm CMOS technology, and its active area is 0.134 mm2 without a loop filter. The power consumption of this CDR circuit is 160 mW for a supply of 1.5 V. A modified interpolation voltage-controlled oscillator is presented, which covers from 4.9 to 10.2 GHz. A quadrature divider is used to generate accurate quadrature clocks.

Clock- and Data-Recovery Circuit With Independently Controlled Eye-Tracking Loop for High-Speed Graphic DRAMs

An independently controlled eye-tracking clock- and data-recovery (CDR) circuit that achieves enhanced high-frequency jitter tolerance is presented in this brief. In the proposed CDR, a data-tracking loop compensates interchannel timing skews and rejects low-frequency jitter of the data, and an eye-tracking loop tracks asymmetric jitter distribution and high-frequency jitter of the data to enhance high-frequency jitter tolerance. This can be achieved by independently controlling two loops in the digital domain. The CDR is implemented using an 0.18- μm CMOS process, and a bit error rate of less than 10-12 was achieved for a data rate up to 5.8 Gb/s using a 231 - 1 pseudorandom binary-sequence input.

Merged Clock Data Recovery and 24-GHz LO Generation Circuit for Crystalless Transcseiver

A fully integrated merged 400-Mb/s clock data recovery (CDR) local oscillator (LO) generation circuit that provides both a 24-GHz local oscillation signal for an up-conversion mixer in a transmitter and a 400-MHz sampling clock for an ADC in a receiver for a crystalless wireless transceiver is demonstrated. The phase noise of the 24-GHz LO signal is -89 dBc/Hz at 1-MHz offset for a 400-Mb/s pseudo random binary sequence (PRBS) 231 - 1 input. This first report of phase noise for a CDR is more than acceptable for amplitude shift-keying wireless communication systems with a square-law detector that is immune to the phase noise. The jitter of 400-MHz recovered clock is 2.6-ps rms (0.1% UI) for a PRBS 231 - 1 input. The jitter performance is the best among the similar data rate (~400 Mb/s) CDRs. The CDR bit error rate is less than 10-13.

Power Optimization of an 11.75-Gb/s Combined Decision Feedback Equalizer and Clock Data Recovery Circuit in 0.18-$\mu\hbox{m}$ CMOS

An 11.75-Gb/s combined decision feedback equalizer (DFE) and clock data recovery circuit in a 0.18-μm CMOS is presented. Various techniques are applied to reduce the chip power consumption. In particular, the feedback path of the DFE is merged with an Alexander phase detector (PD). An analysis on the speed requirements of various blocks in the PD and DFE circuits is performed to determine the optimum power dissipation of each one. It is shown that the chip power consumption is reduced by 31% compared to a conventional design. The chip is capable of equalizing copper cable channels with up to 12-dB loss at the 5.875-GHz Nyquist frequency and consumes 101 mW (not including output buffers) with a 1.8-V supply voltage.

A 1.0–4.0-Gb/s All-Digital CDR With 1.0-ps Period Resolution DCO and Adaptive Proportional Gain Control

This paper describes the design and implementation of an all-digital clock and data recovery circuit (ADCDR) for multigigabit/s operation. The proposed digitally-controlled oscillator (DCO) incorporating a supply-controlled ring oscillator with a digitally-controlled resistor (DCR) generates wide-frequency-range multiphase clocks with fine resolution. With an adaptive proportional gain controller (APGC) which continuously adjusts a proportional gain, the proposed ADCDR recovers data with a low-jitter clock and tracks large input jitter rapidly, resulting in enhanced jitter performance. A digital frequency-acquisition loop with a proportional control greatly reduces acquisition time. Fabricated in a 0.13-μm CMOS process with a 1.2-V supply, the ADCDR occupies 0.074 mm2 and operates from 1.0 Gb/s to 4.0 Gb/s with a bit error rate of less than 10-14. At a 3.0-Gb/s 231 - 1 PRBS, the measured jitter in the recovered clock is 3.59 psrms and 29.4 pspp, and the power consumption is 11.4 mW.

An Injection-Controlled 10-Gb/s Burst-Mode CDR Circuit for a 1G/10G PON System

As a future passive optical network (PON) system, the 10 Gigabit Ethernet PON (10G-EPON) has been standardized in IEEE 802.3av. As conventional Gigabit Ethernet PON (GE-PON) systems have already been widely deployed, 1G/10G co-existence technologies are strongly required for the next system. A gated voltage-controlled-oscillator (G-VCO)-based 10-Gb/s burst-mode clock and data recovery (CDR) circuit is presented for a 1G/10G co-existence PON system. It employs two new circuits to improve jitter transfer and provide tolerance to 1G/10G operation. An injection-controlled jitter-reduction circuit reduces output-clock jitter by 7 dB from 200-MHz input data jitter while keeping a short lock time of 20 ns. A frequency-variation compensation circuit reduces frequency mismatch among the three VCOs on the chip and offers large tolerance to consecutive identical digits. With the compensation, the proposed CDR circuit can employ multi VCOs, which provide tolerance to the 1G/10G co-existence situation. It achieves error-free (bit-error rate < 10 -12 ) operation for 10-G bursts following bursts of other rates, obviously including 1G bursts. It also provides tolerance to a 256-bit sequence without a transition in the data, which is more than enough tolerance for 65-bit CIDs in the 64B/66B code of 10 Gigabit Ethernet.

A 3-GHz Serial ATA Spread-Spectrum Clock Generator Employing a Chaotic PAM Modulation

In this paper, we propose a prototype of a spread-spectrum clock generator which is the first known specifically meant generator for 3-GHz Serial Advanced Technology Attachment II (SATA-II) applications. A further innovative aspect of our prototype is that it takes advantage of a chaotic pulse-amplitude modulation as driving signal, instead of a triangular signal as in all spread-spectrum generators proposed so far in the literature for SATA-II. In this way, we are able to obtain the optimal theoretical electromagnetic-interference reduction by avoiding the periodicity of the modulated clock and completely flattening the peaks in the power spectral density. We also show that, despite the fact that such an unconventional aperiodic modulating signal is used, the clock can be recovered by exploiting a standard clock and data recovery circuit at the receiver side of the SATA-II bus. The circuit prototype has been implemented in 0.13-μm CMOS technology and achieves a peak reduction greater than 14 dB measured at RBW = 100 kHz, which is better than any other prototypes presented in the literature. The estimated random jitter is 5.4 ps <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">rms</sub> , while the chip active area is 0.27 0.78 × mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the power consumption is as low as 14.7 mW.

5/10-Gb/s Burst-Mode Clock and Data Recovery Based on Semiblind Oversampling for PONs: Theoretical and Experimental

In this paper, we demonstrate a 5/10-Gb/s burst-mode clock and data recovery circuit (BM-CDR) for passive optical network (PON) applications. The BM-CDR is based on a phase-tracking oversampling (semiblind) CDR circuit operated at twice the bit rate and a clock phase aligner that makes use of a simple phase-picking algorithm for automatic clock phase acquisition. The design provides low latency and fast response without requiring a reset signal from the network layer. We experimentally test the proposed BM-CDR in a 20-km PON uplink. The BMCDR achieves a bit error rate (BER) <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-10</sup> and packet loss ratio (PLR) <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-6</sup> while featuring: 1) instantaneous (0 preamble bit) phase acquisition for any phase step (±27π rad) between successive bursts; 2) BER and PLR sensitivities of -24.2 and -25.4 dBm, respectively; 3) negligible burst-mode sensitivity penalty of 0.8 dB; 4) frequency acquisition range of 242 MHz; 5) consecutive identical digit (CID) immunity of 3100 bits; and 6) dynamic range of 3 dB. With the instantaneous phase acquisition, we predict the physical efficiency of the upstream PON traffic to be 99%. We also present a unified probabilistic theory for conventional CDRs, N times oversampling CDRs in either time or space, and BM-CDRs built from oversampling CDRs. This theory can quantitatively explain the performance of these circuits in terms of the BER and PLR. The theoretical model accounts for the following parameters: 1) silence period, including phase step and CIDs, between consecutive packets; 2) finite frequency offset between the sampling clock and data rate; 3) preamble length; 4) jitter on the sampling clock; and 5) pattern correlator error resistance. On the basis of this theory, we perform a comprehensive theoretical analysis to assess the tradeoffs between these parameters, and compare the results experimentally to validate the theoretical model.

A 5 Gbps 0.13 $\mu$m CMOS Pilot-Based Clock and Data Recovery Scheme for High-Speed Links

This paper presents a pilot-based clock and data recovery (CDR) technique for high-speed serial link applications where a low-amplitude clock signal, i.e., a pilot, is added to the transmit signal. The clock tone is extracted at the receiver using an injection-locked oscillator and is used to drive the receiver front-end samplers. The performance of the CDR technique is demonstrated using a 5 Gbps differential receiver fabricated in a 0.13 μm IBM CMOS technology. The clock and data recovery circuit implementation has an area of 0.171 mm2 and consumes 11.75 mA from a 1.5 V supply voltage at 5 Gbps. The recovered clock peak-to-peak and RMS jitter at 5 Gbps are less than 10 ps (5%UI) and 1.6 ps (0.8%UI), respectively with an effective CDR loop bandwidth of approximately 28 MHz at a bit-error rate (BER) of 10-12 . The proposed technique simplifies the CDR design and provides data and inter-symbol interference (ISI) independent performance with a small ≈5% pilot voltage overhead to the transmitted data signal.

Design and Performance of 10 Gb/s Optical Receiver in 50-GHz DWDM Transmission over 40-km SSMF

This paper describes the design of 10 Gb/s optical receiver, which consists of an Avalanche Photo Detector (APD) and a Clock &amp; Data Recovery (CDR) circuit. All components are successfully integrated onto the 4-layered FR-4 PCB, using two types of signal paths: di®erential microstrip and single-ended CB-CPW. Their dimensions are optimally chosen for matching impedance, according to the ADS simulations. The receivers performance has been evaluated under 3 impairments: jitter, interchannel crosstalk and fiber dispersion. The Periodic Jitter (PJ) is added to analyze histograms and measure the receivers jitter tolerance. The crosstalk and dispersion effects on eye-diagram are demonstrated via the testbed of 50-GHz Dense Wavelength Division Multi-plexing (DWDM) transmission over 40-km Standard Single Mode Fiber (SSMF). The measured jitter tolerance proves that this receiver can pass the SONET (Synchronous Optical NETwork) mask standard with Bit Error Rate (BER) below 10-12. The recovered eye-diagrams show that this design can reduce both crosstalk and dispersion e®ects. The power penaltyof this receiver is determined from the BER plot to be within 2-dB standard limit.

A 2.5-Gb/s fully-integrated, low-power clock and recovery circuit in 0.18-μm CMOS

Based on the devised system-level design methodology, a 2.5-Gb/s monolithic bang-bang phase-locked clock and data recovery (CDR) circuit has been designed and fabricated in SMIC's 0.18-μm CMOS technology. The Pottbäcker phase frequency detector and a differential 4-stage inductorless ring VCO are adopted, where an additional current source is added to the VCO cell to improve the linearity of the VCO characteristic. The CDR has an active area of 340 × 440 μm2, and consumes apower of only about 60 mW from a 1.8 V supply voltage, with an input sensitivity of less than 25 mV, and an output single-ended swing of more than 300 mV It has a pull-in range of 800 MHz, and a phase noise of −111.54 dBc/Hz at 10 kHz offset. The CDR works reliably at any input data rate between 1.8 Gb/s and 2.6 Gb/s without any need for reference clock, off-chip tuning, or external components.

다중점 위상검출기를 이용한 클럭 및 데이터 복원회로 설계

본 논문에서는 다중점 위상검출기(Phase detector: PD)를 이용한 1Gbps 클럭 및 데이터 복원(Clock and data recovery: CDR)회로를 제안한다. 제안된 위상검출기는 데이터의 천이 모서리와 클럭의 상승/하강 모서리 3점을 비교하여 up/down 신호를 생성한다. 기존의 위상검출기 회로는 클럭 주기의 배수 만큼의 up/down 펄스폭을 갖는 출력으로 전압제어발진기(Voltage controlled oscillator: VCO)를 조절하는 펄스폭변조(Pulse width modulation: PWM)방식을 사용한다. 제안된 위상검출기 회로는 클럭 반주기만큼의 up/down 펄스폭을 갖는 출력으로 전압제어발진기를 조절하는 펄스수변조(Pulse number modulation: PNM)방식을 사용하여, 전압제어발진기를 미세하게 조절함으로써 지터를 줄일 수 있다. 제안된 위상검출기를 이용한 클럭 및 데이터 복원회로는 1Gbps의 전송률을 갖는 231-1개의 랜덤 데이터를 이용하여 테스트되었고, 지터와 전력소비는 각각 7.36ps와 12mW로 저전력, 적은 지터의 특징을 보였다. 제안된 회로는 0.18um CMOS 공정에서 1.8V 전원으로 설계되었다. The 1Gbps clock and data recovery (CDR) circuit using the proposed multi-point phase detector (PD) is presented. The proposed phase detector generates up/down signals comparing 3-point that is data transition point and clock rising/falling edge. The conventional PD uses the pulse width modulation (PWM) that controls the voltage controlled oscillator (VCO) using the width of a pulse period's multiple. However, the proposed PD uses the pulse number modulation (PNM) that regulates the VCO with the number of half clock cycle pulse. Therefore the proposed PD can controls VCO preciously and reduces the jitter. The CDR circuit is tested using 1Gbps <TEX>$2^{31}-1$</TEX> pseudo random bit sequence (PRBS) input data. The designed CDR circuit shows that is capable of recovering clock and data at rates of 1Gbps. The recovered clock jitter is 7.36ps at 1GHz and the total power consumption is about 12mW. The proposed circuit is implemented using a 0.18um CMOS process under 1.8V supply.

The Design of Serial ATA Bus Control Chip

In a PC system, External storage interface is still a bottleneck in spite of its continuous improving performance, in contrast to the fast development of CPU, memory, graphic chips. The transfer rate in ATA protocol has been improved drastically from the beginning 3.3MB/s to current 133MB/s, but the plate electrode of a parallel interface is inevitably puzzled by clock skew, which limit the increasing of frequency and transfer rate can not be improved. Serial ATA protocol is compatible with Parallel ATA protocol in software layer. Its transfer rate is improved greatly due to serial interface with embedded clock. This paper will discuss the differences between Parallel ATA protocol and serial ATA protocol, and describe the hierarchical classification of serial ATA protocol model. Last a design for HPT183, a parallel/serial ATA bridge connection chip will be put forward. In high speed serial interface integrated circuit design, the design of high speed serial data recovery circuit is a troublesome task. In this paper an all-digital high speed serial data recovery circuit module for 1.5bps SATA interface implement is introduced. In contract to other design made from analog circuit, this all-digital circuit is an easily implement design and it has lower power consumption and smaller area. This circuit is being implemented in HPT183 chip which is designed and manufactured using a 0.18um CMOS process. At the end the test performance index for this chip is also provided.

5 Gbit/s burst-mode experiments for high split extended reach PONs

Burst-mode (BM) experiments at 5 Gbit/s on optically amplified high split passive optical networks (PONs) with extended reach are presented. The evaluated systems include a DC-coupled burst-mode receiver (BM-Rx) integrated with a BM clock data recovery (BM-CDR) circuit, an inline EDFA and two branches of BM transmitters (BM-Txs). High optical power budget combined with very short guard time and receiver settling time was achieved.

Packaging in IBIS-AMI Technology

As serial links become faster and more complex, it is ever more challenging to model the silicon in an accurate and efficient manner. Traditional IBIS package models are simply not accurate enough and lack the bandwidth required for high-speed serial channels. The IBIS Algorithmic Modeling Interface (AMI) is a promising standard that is able to accurately model drivers and receivers that include equalizers and clock data recovery circuits. The introduction of the AMI modeling standard presents the opportunity to combine accurate driver and receiver models with high quality scattering parameter and W-element models of the passive IC, package, and PCB structures. In this paper we explore simulation with AMI models driving accurate high-bandwidth channel models of packages and printed circuit boards for robust simulation of high-speed serial systems. We also use these simulations to investigate the effects of variability in the manufactured channel.