Data Recovery Circuit Research Articles

A 2.5-Gb/s DLL-Based Burst-Mode Clock and Data Recovery Circuit With <inline-formula> <tex-math notation="LaTeX">$4\times$ </tex-math></inline-formula> Oversampling

In this brief, a delay-locked loop (DLL)-based burst-mode clock and data recovery (BMCDR) circuit using a $4\times$ oversampling technique is realized for passive optical network. With the help of DLL to track the input phase, the proposed circuit can recover the burst-mode data in a short acquisition time and achieve large jitter tolerance. In addition, a 2.5-GHz four-phase clock generator is embedded in the chip. Implemented with a 0.18- $\mu{\rm m}$ CMOS technology, experiment shows that the acquisition time can be accomplished in the time of 31 bits. Incoming 2.5-Gb/s input data of $2^{31}{-}1$ pseudorandom binary sequence, the retimed data has a root-mean-square jitter of 8.557 ps and a peak-to-peak jitter of 32.0 ps, and the measured bit error rate is less than $10^{-10}$ . The area of the whole chip is 1.4 $\,\times\,$ 1.4 ${\rm mm}^{2}$ , where the BMCDR circuit core occupies 0.81 $\,\times\,$ 0.325 ${\rm mm}^{2}$ . The total power consumption is 130 mW from a 1.8 V supply voltage.

A 6‐Gbps/lane receiver for a clock‐forwarded link in 65‐nm CMOS process

SummaryFor a 6‐Gbps/lane clock‐forwarded link, a wireline receiver has been developed. The phases of the sampling clocks are aligned to the center of the input data eye by a clock and data recovery (CDR) circuit. In the CDR circuit, the sampling clock phases are rotated by a phase rotating phase locked loop (PLL). A three‐tap decision feedback equalizer (DFE) compensates for the loss of cable together with a continuous‐time linear equalizer (CTLE) to ensure sufficient eye opening for the CDR circuit to find the optimum sampling phase. The DFE coefficients are adaptively calculated based on the data and edge samples. Implemented in a 65‐nm CMOS process, the three‐lane 6‐Gbps/lane receiver for a clock‐forwarded link occupies 0.63 mm2 including pads and consumes 288 mA from a 1.2‐V supply. Copyright © 2015 John Wiley & Sons, Ltd.

A 10-Gb/s, 1.24 pJ/bit, Burst-Mode Clock and Data Recovery With Jitter Suppression

A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UI pp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 ps rms . The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm 2 only. It dissipates 12.4 mW from 1 V supply.

A Burst-Mode Digital Receiver With Programmable Input Jitter Filtering for Energy Proportional Links

A full-rate burst-mode receiver that achieves fast on/off operation needed for energy-proportional links is presented. By injecting input data edges into the oscillator embedded in a classical Type-II digital clock and data recovery (CDR) circuit, the proposed receiver achieves instantaneous phase-locking and input jitter filtering simultaneously. In other words, the proposed CDR combines the advantages of conventional feed-forward and feedback architectures to achieve energy-proportional operation. By controlling the number of data edges injected into the oscillator, both the jitter transfer bandwidth and the jitter tolerance corner are accurately controlled. The feedback loop also corrects for any frequency error and helps improve CDR's immunity to oscillator frequency drift during the power-on and -off states. This also improves CDR's tolerance to consecutive identical digits present in the input data. Fabricated in a 90 nm CMOS process, the prototype receiver instantaneously locks onto the very first data edge and consumes 6.1 mW at 2.2 Gb/s. Owing to its short power-on time, the receiver's energy efficiency varies only from 2.77 pJ/bit to 3.87 pJ/bit when the effective data rate is varied from 0.44 Gb/s to 2.2 Gb/s. Input sensitivity of the receiver is 36 mV for a BER of 10 -12 .

A 5 Gb/s low area CDR for embedded clock serial links

A multi-standard compatible clock and data recovery circuit (CDR) with a programmable equalizer and wide tracking range is presented. Considering the jitter performance, tracking range and chip area, the CDR employs a first-order digital loop filter, two 6-bit DACs and high linearity phase interpolators to achieve high phase resolution and low area. Meanwhile the tracking range is greater than ±2200 ppm, making this proposed CDR suitable for the embedded clock serial links. A test chip was fabricated in the 55 nm CMOS process. The measurements show that the test chip can achieve BER < 10−12 and meet the jitter tolerance specification. The test chip occupies 0.19 mm2 with a 0.0486 mm2 CDR core, which only consumes 30 mW from a 1.2 V supply at 5 Gb/s.

A novel digital phase interpolation control for clock and data recovery circuit

In this express, we present a new architecture of digital phase interpolation (PI) controller with clock and data loops, which can greatly reduce the jitter of recovery clock by reducing the probability of the coarse phase jumping and interpolating among several fine phases. A demo design was implemented using 0.13 µm CMOS technology for verification, and the simulation results demonstrate that the recovered clock of the presented architecture has a peak to peak jitter no more than 29 ps under 2.5 Gbps received data, which shows no coarse phase dithering happening. The area of this proposed PI controller is only 0.1 mm2.

A 10-Gb/s Low Jitter Single-Loop Clock and Data Recovery Circuit With Rotational Phase Frequency Detector

This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71- mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . With input 10-Gb/s data of a 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> -1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 μs. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage.

DESIGN AND IMPLEMENTATION OF A HIGH SPEED CLOCK AND DATA RECOVERY DELAY LOCKED LOOP USING SC FILTER

This paper presents the design of a clock and data recovery circuit having a high data rate of 9.95328 Gb/s by using delay locked loop with Switched Capacitor (SC) filter to improve the jitter transfer function and jitter tolerance as it has high Q and low center frequency. From the results it is seen that the besides the conventional DLL circuit , the circuit using SC filter of fc= 311.04 MHz and Q=500 provides very low cut off frequency.

A Throughput-Optimized Optical Network for Data-Intensive Computing

Data-intensive computing increasingly involves operations at the scale of an entire computing system, requiring quick and efficient processing of massive datasets. In this article, the authors present a circuit-switched network architecture, together with requisite optical-switch and burst-mode transceiver technology, designed to support demanding graph algorithms in a distributed-memory system. The proposed optical network, configured as multiple planes of high-radix wavelength-division-multiplexed (WDM) switches, offers tremendous path diversity and is designed to deliver up to 10 terabytes per second of node bandwidth and predictable performance under heavy load with latencies well under a microsecond. With the optical core switch, the authors overcome pin-count and power-dissipation limitations of electrical networks with comparable bandwidth. To achieve this, they are developing new hardware, including nanosecond-scale silicon photonic switches with flip-chip-attached optical amplifiers, low-power parallel WDM transceivers operating at about 20-Gbps per channel, with burst-mode clock and data recovery circuits in advanced CMOS for link retraining in tens of nanoseconds. Network simulations predict that the proposed system could achieve graph performance on par with today's leading supercomputers, and its limited power consumption would result in several orders of magnitude of efficiency improvements that could allow the system to fit within a few racks.

Enhancement of sensitivity of RF modules for wireless health care and home security systems

ABSTRACTAn effective way to enhance the sensitivity of an RF module for wireless health care (and home security) products is reported. The RF module (followed by a microcontroller unit) consists of an RF front‐end, an radio frequency integrated circuit (RFIC), and a baseband data recovery circuit (DRC). The RF front‐end comprises a power amplifier (PA) output matching network to enhance the output power of the PA, and a low‐noise amplifier (LNA) input matching network to improve the sensitivity of the LNA. The baseband DRC comprises a multiple feedback low‐pass filter to suppress out‐of‐channel noise/interference, and a comparator for rail‐to‐rail digital data recovery. This in turn results in an enormous enhancement of sensitivity (or operation range) of wireless health care (and home security) products equipped with this RF module. Compared with an RF module without the proposed DRC, a 10 dB improvement in sensitivity (from −106 to −116 dB) is achieved. Furthermore, RF field test of a wireless health care product (both with and without the proposed DRC in its RF module) shows a more than 100% enhancement in the wireless operation range (from 150 m to more than 300 m) and a 10‐dB improvement in adjacent channel selectivity. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:2563–2568, 2014

A Low-Energy Rate-Adaptive Bit-Interleaved Passive Optical Network

Energy consumption of customer premises equipment (CPE) has become a serious issue in the new generations of time-division multiplexing passive optical networks, which operate at 10 Gb/s or higher. It is becoming a major factor in global network energy consumption, and it poses problems during emergencies when CPE is battery-operated. In this paper, a low-energy passive optical network (PON) that uses a novel bit-interleaving downstream protocol is proposed. The details about the network architecture, protocol, and the key enabling implementation aspects, including dynamic traffic interleaving, rate-adaptive descrambling of decimated traffic, and the design and implementation of a downsampling clock and data recovery circuit, are described. The proposed concept is shown to reduce the energy consumption for protocol processing by a factor of 30. A detailed analysis of the energy consumption in the CPE shows that the interleaving protocol reduces the total energy consumption of the CPE significantly in comparison to the standard 10 Gb/s PON CPE. Experimental results obtained from measurements on the implemented CPE prototype confirm that the CPE consumes significantly less energy than the standard 10 Gb/s PON CPE.

A Low-Power CMOS Receiver for 1.25 Gb/s Over 1- mm SI-POF Links

This paper presents an optical receiver for short-reach applications through low-cost plastic optical fiber. The limited bandwidth caused by the fiber and the external photodiode is compensated by a new adaptive equalizer based on the spectrum balancing technique. A clock and data recovery circuit is included that minimizes jitter and metastability using a new multilevel bang-bang architecture. The prototype, implemented in a standard 0.18-μm CMOS process, achieves 1.25 Gb/s with a power of 107 mW at only 1 V.

A 26–28-Gb/s Full-Rate Clock and Data Recovery Circuit With Embedded Equalizer in 65-nm CMOS

This paper presents a power and area efficient approach to embed a continuous-time linear equalizer (CTLE) within a clock and data recovery (CDR) circuit implemented in 65-nm CMOS. The merged equalizer/CDR circuit achieves full-rate operation up to 28 Gb/s while drawing 104 mA from a 1-V supply and occupying 0.33 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Current-mode-logic (CML) circuits with shunt peaking loads using customized differential pair layout are used to maximize circuit bandwidth. To minimize the area penalty, differential stacked spiral inductors (DSSIs) are employed extensively. A novel and practical methodology is introduced for designing DSSIs based on single-layer inductors provided in foundry process design kits (PDK). The DSSI design increases the inductance density by over 3 times and the self-resonance frequency by 20% compared to standard single-layer inductors in the PDK. The measured BER of the recovered data by the CDR is less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> at 27 Gb/s for 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">11</sup> -1 400 mV PP pseudo-random binary sequence (PRBS) as input data. The measured rms jitter of the recovered clock and data are 1.0 and 2.6 ps, respectively. The CDR is able to lock to inputs ranging from 26 to 28 Gb/s with 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">9</sup> -1 PRBS pattern. Measurement results show that with the equalizer enabled, the CDR can recover a 26-Gb/s 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">7</sup> -1 PRBS data with BER ≤ 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> after a channel with 9-dB loss at 13 GHz.

Linearization Technique for Binary Phase Detectors in a Collaborative Timing Recovery Circuit

A multichannel clock and data recovery (CDR) circuit that employs binary phase detectors (PDs) yet achieves linear loop dynamics is presented. The proposed CDR recovers the linear information of phase errors by exploiting its collaborative timing recovery architecture. Since the collaborative CDR combines the PD outputs of the multiple data streams, a deliberate phase offset can be added to each PD to realize a high-rate oversampling PD without additional PDs. The analysis shows that there exists an optimal spacing between these deliberate phase offsets that maximizes the linearity of the proposed PD for given jitter conditions. Under these conditions, the loop dynamics of a linear, second-order CDR model agree well with the simulated responses even with a finite latency difference between the proportional and integral control paths. The linearized characteristics of the PD and the overall CDR designed for 45-nm CMOS technology are, respectively, verified by using a time-step accurate behavioral simulation.

Power-Reduction Technique Using a Single Edge-Tracking Clock for Multiphase Clock and Data Recovery Circuits

In this brief, a 1/10-rate bang-bang phase detector (BBPD) using a single edge-tracking clock and a phase interpolator (PI)-based clock and data recovery (CDR) circuit with the proposed BBPD is presented. While a typical 1/N-rate BBPD uses 2N clocks for data sampling and edge tracking, the proposed 1/N rate BBPD uses only N + 1 clocks, N for data sampling and 1 for edge tracking. The power consumption of the CDR with the proposed 1/N-rate BBPD is decreased. The reduction of the jitter tracking bandwidth of the CDR is compensated by the proposed data-encoding method. The 1/10-rate PI-based CDR with the proposed BBPD is implemented using a 0.18-μm CMOS process technology. The bit error ratio of less than 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> is achieved at the effective data rate of 6.93 Gb/s using encoded 2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">31</sup> - 1 pseudorandom binary-sequence data inputs. The power consumption of the CDR is 29.4 mW at the supply voltage of 1.8 V and the active area is 0.117 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The effective power efficiency of the CDR is 4.24 mW/Gb/s.

A Reference-Less Clock and Data Recovery Circuit Using Phase-Rotating Phase-Locked Loop

A reference-less half-rate digital clock and data recovery (CDR) circuit employing a phase-rotating phase-locked loop (PRPLL) as phase interpolator is presented. By implementing the proportional control in phase domain within the PRPLL, the proposed CDR decouples jitter transfer (JTRAN) bandwidth from jitter tolerance (JTOL) corner frequency, eliminates jitter peaking, and removes JTRAN dependence on bang-bang phase detector gain. Fabricated in a 90 nm CMOS process, the prototype CDR achieves error-free operation (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) with PRBS data sequences ranging from PRBS7 to PRBS31. At 5 Gb/s, it consumes 13.1 mW power and achieves a recovered clock long-term jitter of 5.0 ps rms/44.0 ps pp when operating with PRBS31 input data. The measured JTRAN bandwidth is 2 MHz and JTOL corner frequency is 16 MHz. The CDR is tolerant to 110 mV pp of sinusoidal noise on the DCO supply voltage at the worst case noise frequency of 7 MHz. At 2.5 GHz, the PRPLL consumes 2.9 mW and achieves -134 dBc/Hz phase noise at 1 MHz frequency offset. The differential and integral non-linearity of its digital-to-phase transfer characteristic are within ±0.2 LSB and ±0.4 LSB, respectively.

Fast Synchronization 3R Burst-Mode Receivers for Passive Optical Networks

This paper gives a tutorial overview on high speed burst-mode receiver (BM-RX) requirements, specific for time division multiplexing passive optical networks, and design issues of such BM-RXs as well as their advanced design techniques. It focuses on how to design BM-RXs with short burst overhead for fast synchronization. We present design principles and circuit architectures of various types of burst-mode transimpedance amplifiers, burst-mode limiting amplifiers and burst-mode clock and data recovery circuits. The recent development of 10 Gb/s BM-RXs is highlighted also including dual-rate operation for coexistence with deployed PONs and on-chip auto reset generation to eliminate external timing-critical control signals provided by a PON medium access control. Finally sub-system integration and state-of-the-art system performance for 10 Gb/s PONs are reviewed.

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

A 1.5–5.0 Gb/s clock and data recovery circuit with dual-PFD phase-rotating phase locked loop

A low jitter clock and data recovery with a single edge sensing Bang-Bang PD

This letter describes a low jitter clock and data recovery (CDR) circuit with a modified bang-bang phase detector (BBPD). The proposed PD senses the phase relationship using a single edge of input data to reduce ripples in the VCO control voltage. A 2.5Gbps CDR circuit with a proposed BBPD has been designed and compared with conventional BBPD using 0.13μm CMOS technology. Measured results reveal that proposed CDR shows the peak-to-peak jitter of 17ps on 25−1 PRBS input pattern compared to 26ps with the CDR with a conventional BBPD. The proposed CDR can be best applied to 8B10B encoded input data. Power consumption can also be saved by about 3mW with the proposed BBPD.

단일 에지 이진위상검출기를 사용한 저 지터 클록 데이터 복원 회로 설계

본 논문은 CDR회로의 지터 감소를 위해 변형된 이진 위상검출기(뱅뱅위상 검출기- BBPD) 회로를 제안하였다. 제안된 PD는 하나의 에지를 사용함으로써 전압리플을 줄여, 제안한 PD를 적용하여 설계한 CDR회로는 감소된 지터 특성을 보였다. CMOS 0.13um 공정을 사용하여 설계하였고 제안한 위상검출기를 포함하는 클럭데이터 복원회로는 모의실험결과 16.9mW 전력소비에 peak-peak 지터는 10.96ps, rms 지터는 0.89ps을 보였다. This paper describes a modified binary phase detector (Bang-Bang phase detector - BBPD) for jitter reduction in clock and data recovery (CDR) circuits. The proposed PD reduces ripples in the VCO control voltage resulting in reduced jitter for CDR circuits. A 2.5 Gbps CDR circuit with a proposed BBPD has been designed and verified using Dongbu <TEX>$0.13{\mu}m$</TEX> CMOS technology. Simulation shows the CDR with proposed PD recovers data with peak-to-peak jitter of 10.96ps, rms jitter of 0.86ps, and consumes 16.9mW.