Datapath Modules Research Articles

Research the SDRAM Controller Based on FPGA

A global SDRAM controller was designed based on FPGA. The major components of the controller include the interface control module, the command generation module, the data path module, and the source program simulation using Quartus II. From the simulation results, the soft core of the SDRAM controller could complete the mode setting, normal R/W operation, and auto-refresh function. It could easily meet different needs by simple modification, and it is much more flexible and programmable.

Computational architectures for sonar array processing in autonomous rovers

This paper presents design of novel embedded computational architectures for real time, in-motion mapping based on ultrasound sensors for use in resource constrained autonomous rovers. Autonomous rovers are a class of real time systems that are constrained for size, weight, on-board computational resources and power. Embedded computing architectures designed for implementing the mapping and navigational algorithms must optimize the use of these resources. In the process of map generation, raw sensor data obtained from an array of ultrasound sensors is filtered for sensor noise using probabilistic sensor model, and probabilistic data fusion methods are employed for spatial and temporal correlation of data for improving the map. In this paper, we present a System-on-Chip design based design space exploration of embedded computational architectures for implementation on field programmable gate arrays. We seek to exploit system level, region level and sensor level parallelism in the mapping algorithm for enhancing the throughput. Design space exploration is carried out by employing existing soft core processors, designing custom co-processors and data path modules and integrating them using parallel and pipelined data flow approaches. Results of mapping a test area on all the architectures are compared to characterize the performance and suitability of the proposed architectures.

Design of an efficient and faster SDRAM Controller

In this paper Double data rate synchronous dynamic (DDR SDRAM) accessing of memory and controller are designed in such a way that it supports double data transfer rate. To guarantee that the system works as intended, the memory controller is configured such that all the real-time requirements of all sharing applications are satisfied. A fully functional DDRSDRAM controller is designed to perform Read and Write operations on both rising and falling edge (DDR) of clock from the memory by using data path module with double data transfer throughput and bandwidth of the memory. The implementation uses direct clocking for data capture. To improve the access speed controller will generate the control signals at high speed and memory also supposes to access the data very easily. The memory has been designed to access the data by using the CAS and RAS signals in an easy way and controller also has been implemented with double data rate. For a single row different column data can be read at a time so the improvement of 28.57% in the performance of memory accessing.

Cell libraries for robust low-voltage operation in nanometer technologies

The key challenge of wireless sensor nodes is their total power dissipation, hampering their autonomous operation due to limited battery life time. Aggressive voltage scaling reduces both dynamic and leakage power, prolonging the battery life time. The challenges of aggressive voltage scaling into the subthreshold region includes the pronounced effect of process variability and the significantly reduced performance. In this paper, these challenges are addressed by first devising a novel cell library pruning methodology to ensure reliable voltage scaling based on the noise margin criterion. Using the proposed approach, further voltage scaling is possible, enabling more than 20% energy savings as compared to the classic approach of avoiding high fan-in cells and/or complex gates. Then, the design of standard cells for two dedicated design points is presented which considers both the transistor geometry (L, W, and the number of fingers) as well as the cell layout to achieve up to a 3× speed-up as compared to a conventional methodology. The result is also validated in measurement leading to the comparison of a datapath module of slightly better energy efficiency and 3× better performance.

Simulation-Based Functional Test Generation for Embedded Processors

Deterministic functional test pattern generation has been a long-standing open problem, which is an important problem to be solved for both design verification and manufacturing testing. One key in developing a practical functional test pattern generation approach is to avoid the exponential growth of the test generation complexity in terms of the design size. This work proposes a novel functional test generation approach where simulation results are used to guide the generation of additional tests. Our methodology avoids the complexity growth issue by converting some modules in a design into simpler and more efficient models. Then, these models are used to facilitate the actual test generation process. We develop two sets of techniques to achieve these conversions: Boolean learning for random logic and arithmetic learning for datapath modules. We demonstrate the effectiveness and discuss the. limitations of these techniques through experiments on benchmark circuits. Last, we validate the overall test generation methodology based on the OpenRISC 1200 microprocessor

Novel Low-Overhead Operand Isolation Techniques for Low-Power Datapath Synthesis

Power consumption in datapath modules due to redundant switching is an important design concern for high-performance applications. Operand isolation schemes that reduce this redundant switching incur considerable overhead in terms of delay, power, and area. This paper presents novel operand isolation techniques based on supply gating that reduce overheads associated with isolating circuitry. The proposed schemes also target leakage minimization and additional operand isolation at the internal logic of datapath to further reduce power consumption. We integrate the proposed techniques and power/delay models to develop a synthesis flow for low-power datapath synthesis. Simulation results show that the proposed operand isolation techniques achieve at least 40% reduction in power consumption compared to original circuit with minimal area overhead (5%) and delay penalty (0.15%)

Power-efficient dual-rate optical transceiver

A dual-rate (2 Gbit/s and 100 Mbit/s) optical transceiver designed for power-efficient connections within and between modern high-speed digital systems is described. The transceiver can dynamically adjust its data rate according to performance requirements, allowing for power-on-demand operation. Dynamic power management permits energy saving and lowers device operating temperatures, improving the reliability and lifetime of optoelectronic-devices such as vertical-cavity surface-emitting lasers (VCSELs). To implement dual-rate functionality, we include in the transmitter and receiver circuits separate high-speed and low-power data path modules. The high-speed module is designed for gigabit operation to achieve high bandwidth. A simpler low-power module is designed for megabit data transmission with low power consumption. The transceiver is fabricated in a 0.5 microm silicon-on-sapphire complementary metal-oxide semiconductor. The VCSEL and photodetector devices are attached to the transceiver's integrated circuit by flip-chip bonding. A free-space optical link system is constructed to demonstrate correct dual-rate functionality. Experimental results show reliable link operation at 2 Gbit/s and 100 Mbit/s data transfer rates with approximately 104 and approximately 9 mW power consumption, respectively. The transceiver's switching time between these two data rates is demonstrated as 10 micros, which is limited by on-chip register reconfiguration time. Improvement of this switching time can be obtained by use of dedicated input-output pads for dual-rate control signals.

Zero-overhead loop controller that implements multimedia algorithms

Multimedia algorithms generally consist of regular repetitive loop constructs. The authors present a novel control unit design for implementing such loop intensive algorithms. The proposed architecture, termed a zero-overhead loop controller (ZOLC) exploits the regularity of computations, which is a common characteristic of multimedia algorithms, in order to efficiently support the corresponding datapaths. The ZOLC controls the operations in datapath modules by activating/deactivating their corresponding controlling FSMs. Algorithmic flow dependencies, which determine the appropriate loop sequencing, are mapped onto a look-up table (LUT). For another algorithm to execute, only the LUT context and the FSM configurations have to be reprogrammed, assuming a generic datapath. Thus, partial reconfiguration possibilities to implement multimedia algorithms on programmable platforms can be exploited. As proof-of-concept, implementations of algorithms of the multimedia domain are investigated to evaluate the performance of the proposed unit, against other methods of control. Also, a full-search motion estimation processor employing the ZOLC is synthesised. It is shown that the ZOLC provides flexibility by supporting various algorithms of the multimedia field with performance improvements of up to 2.1 over conventional control methods.

A scalable algorithm for RTL insertion of gated clocks based on ODCs computation

We propose a new algorithm for automatic clock-gating insertion applicable at the register transfer level (RTL). The basic rationale of our approach is to eliminate redundant computations performed by temporally unobservable blocks through aggressive exploitation of observability don't care (ODC) conditions. ODCs are efficiently detected from an RTL description by focusing only on data-path modules with easily detectable input unobservability conditions. ODCs are then propagated in the form of logic expressions toward the registers by backward traversal and levelization of the design. Finally, the logic expressions are mapped onto hardware to provide control signals to the clock-gating logic at a reduced cost in area and speed. The technique is characterized by fast processing time, high scalability to large designs, and tight user control on clock-gating overhead. Our approach is compatible with standard industrial design flows, and reduces power consumption significantly with a small overhead in delay and area. Experimental results obtained on a set of industrial RTL designs containing several tens of thousands of gates show average power reductions of around 42%. On the same examples, the application of traditional clock-gating leads to average savings reductions close to 29%.

A scalable algorithm for RTL insertion of gated clocks based on ODCs computation

We propose a new algorithm for automatic clock-gating insertion applicable at the register transfer level (RTL). The basic rationale of our approach is to eliminate redundant computations performed by temporally unobservable blocks through aggressive exploitation of observability don't care (ODC) conditions. ODCs are efficiently detected from an RTL description by focusing only on data-path modules with easily detectable input unobservability conditions. ODCs are then propagated in the form of logic expressions toward the registers by backward traversal and levelization of the design. Finally, the logic expressions are mapped onto hardware to provide control signals to the clock-gating logic at a reduced cost in area and speed. The technique is characterized by fast processing time, high scalability to large designs, and tight user control on clock-gating overhead. Our approach is compatible with standard industrial design flows, and reduces power consumption significantly with a small overhead in delay and area. Experimental results obtained on a set of industrial RTL designs containing several tens of thousands of gates show average power reductions of around 42%. On the same examples, the application of traditional clock-gating leads to average savings reductions close to 29%.

Fast Hierarchical Test Path Construction for Circuits with DFT-Free Controller-Datapath Interface

Hierarchical approaches address the complexity of test generation through symbolic reachability paths that provide access to the I/Os of each module in a design. However, while transparency behavior suitable for symbolic design traversal can be utilized for constructing reachability paths for datapath modules, control modules do not exhibit transparency. Therefore, incorporating such modules in reachability path construction requires exhaustive search algorithms or expensive DFT hardware. In this paper, we discuss a fast hierarchical test path construction method for circuits with DFT-free controller-datapath interface. A transparency-based RT-Level hierarchical test generation scheme is devised for the datapath, wherein locally generated vectors are translated into global design test. Additionally, the controller is examined through the introduced concept of influence tables, which are used to generate valid control state sequences for testing each module through hierarchical test paths. Fault coverage and vector count levels thus attained match closely those of traditional test generation methods, while sharply reducing the corresponding computational cost and test generation time.

Functional vector generation for HDL models using linear programming and Boolean satisfiability

Our strategy for automatic generation of functional vectors is based on exercising selected paths in the given hardware description language (HDL) model. The HDL model describes interconnections of arithmetic, logic, and memory modules. Given a path in the HDL model, the search for input stimuli that exercise the path can be converted into a standard satisfiability (SAT) checking problem by expanding the arithmetic modules into logic gates. However, this approach is not very efficient. We present a new HDL-SAT checking algorithm that works directly on the HDL model. The primary feature of our algorithm is a seamless integration of linear-programming techniques for feasibility checking of arithmetic equations that govern the behavior of data-path modules and SAT checking for logic equations that govern the behavior of control modules. This feature is critically important to efficiency, since it avoids module expansion and allows us to work with logic and arithmetic equations whose cardinality tracks the size of the HDL model. We describe the details of the HDL-SAT checking algorithm in this paper. Experimental results that show significant speedups over state-of-the-art gate-level SAT checking methods are included.

Automatic synthesis of large telescopic units based on near-minimum timed supersetting

In high-performance systems, variable-latency units are often employed to improve the average throughput when the worst-case delay exceeds the cycle time. Traditionally, units of this type have been hand-designed. In this paper, we propose a technique for the automatic synthesis of variable-latency units that is applicable to large data-path modules. We define and study an optimization problem, timed supersetting, whose solution is at the kernel of the procedure for automatic generation of variable-latency units. We contribute a new algorithm for solving timed supersetting in the most difficult case, that is, when the timing behavior of the circuit is expressed through an accurate delay model. The proposed solution overcomes the computational limitations of previous approaches and its robustness is experimentally demonstrated by obtaining high-throughput, variable-latency implementations for all the largest circuits in the Iscas '85 and Iscas '89 benchmark suites, as well as for some realistic, high-performance arithmetic units.

A variable-precision square root implementation for field programmable gate arrays

Applications requiring variable-precision arithmetic often rely on software implementations because custom hardware is either unavailable or too costly to build. By using the flexibility of the Xilinx XC4010 field programmable gate arrays, we present a hardware implementation of square root that is easily tailored to any desired precision. Our design consists of three types of modules: a control logic module, a data path module to extend the precision in 4-bit increments, and an interface module to span multiple chips. Our data path design avoids the common problem of large fan-out delay in the critical path. Cycle time is independent of precision, and operation latency can be independent of interchip communication delays.

LILA: layout generation for iterative logic arrays

A CAD tool, LILA, that generates layouts of both one-dimensional and two-dimensional iterative logic arrays, described in VHDL or schematic structures, is presented. Such a tool is very important because in current industry, the generation of high density iterative logic arrays (such as data paths in microprocessors) is still mainly performed manually, and is a major bottleneck of the design. In LILA, interconnections between modules (i.e., cells) of the array do not need to be between adjacent modules and functions of modules of the array do not need to be identical. Regularity in module functions and interconnections between modules are automatically extracted by the tool. Based on interconnection wire length between modules, layouts of modules and interconnections are optimized in a single step. The signals in each array module are generated in such a way that signals in adjacent modules are perfectly aligned and connected by module abutments. As no global routing or channel routing between modules are necessary, the total layout area and propagation delay between modules are minimal. The proposed system is especially useful for data path modules, bit-level systolic arrays, storage devices, and many other regular structures, and has been actually implemented in a design environment. Extensive experiments have shown that the system has a very good performance and produces layouts of very high density. The tool takes about 1.6 CPU seconds to generate an eight-by-eight array divider on a SUN SPARCstation II. >

Design of clocking schemes in high-level synthesis

This paper describes an performance-driven optimization approach to high-level synthesis of VLSI systems. In particular, it presents a new algorithm to automatically design clocking schemes for digital VLSI systems. An optimization strategy is used to integrate the clocking scheme design process with the rest of the high-level synthesis sub-tasks, such as data path allocation, control allocation, module binding and system partitioning. The main features of our approach are the integration of the clock design with other synthesis activities and an ability to generate asynchronous clocking schemes by partitioning VLSI systems into time-independent modules.