Data Path Control Research Articles

Transformations and resynthesis for testability of RT-level control-data path specifications

In order to remain competitive,a company needs to reduce its product development time,and consequently the development time for prototyping has to be reduced as well.One way to decrease the development time of a product is to synthesize the design description automatically to FPGAs (Field Programmable Gate Arrays).This article describes the experience of implementing a real-time kernel in hardware using VHDL for behavioral and data flow (RTL) description, simulation,synthesis to gate level,back-annotation and programming FPGAs for a prototype.

Transformations and resynthesis for testability of RT-level control-data path specifications

This paper introduces a technique to transform a given register-transfer level (RT-level) design, consisting of control logic and data path, into a functionally equivalent, minimized design which is 100% testable under full-scan at the gate level. The proposed RT-level optimization technique uses the RT-level structure and exploits the interaction between the control and the data path. Our approach maintains the RT-level design hierarchy while performing RT-level transformations of initially specified data path, followed by resynthesis of control using don't cares extracted from the data path. Experiments with several RTL benchmarks demonstrate the effectiveness of the technique in generating fully testable designs. In addition, comparison with logic-level techniques show the advantages of the proposed technique as an optimizing tool to produce circuits with reduced area and delay.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A high level synthesis algorithm including control constraints

Data path synthesis and control part synthesis are strongly interdependent. This fact vindicates a novel approach for early control optimization in terms of the number of commands, while data path is still at the very beginning stage of its synthesis. The scheduling algorithm is based on stochastic searching guided by a cost function to be minimized. In order to take into account the control aspect optimization a simple term is added to the cost function used in the scheduling process. This term is merely a statistical measure of the Control Data Flow Graph regularity, since our conjecture is that the more regular the CDFG, the simpler the Control Part. Moreover, this simple extra measure of regularity during scheduling permits to perform scheduling and binding, in sequence, without decreasing the solution quality.

Design of clocking schemes in high-level synthesis

This paper describes an performance-driven optimization approach to high-level synthesis of VLSI systems. In particular, it presents a new algorithm to automatically design clocking schemes for digital VLSI systems. An optimization strategy is used to integrate the clocking scheme design process with the rest of the high-level synthesis sub-tasks, such as data path allocation, control allocation, module binding and system partitioning. The main features of our approach are the integration of the clock design with other synthesis activities and an ability to generate asynchronous clocking schemes by partitioning VLSI systems into time-independent modules.

Control circuit synthesis system

AbstractThis paper presents a systematic and automatic synthesis procedure based on the behavior specifications and the data path. The system automatically determines the control of the data path components and quasiminimizes the hardware complexity of the control circuit. The major contents are as follows: (1) the control circuit is of the Mealy‐type finite‐state sequential circuit; (2) data path is analyzed, and the components to be controlled and the control signals are determined in order to realize the basic manipulations such as operation and data transfer described in the behavior specifications; (3) concurrent operation of the data path is considered, and the control signals to the nonconcurrent component are encoded or shared; (4) the state used in the specification is encoded into the internal states of the control circuit. The code is determined so that the number of product terms in the state‐transition function or the control output function is quasi‐minimized; (5) based on the result of (3) and (4), the state‐transition function and the control output function representing the data path control condition are determined; (6) the state‐transition function and the control output function are realized by PLA and other devices.

An Integrated Modular and Standard Cell VLSI Design Approach

An advanced design method integrating different design approaches is proposed which can attain an optimized chip design within an acceptable turnaround time (TAT). Logic VLSI networks can be generally partitioned into data path logic, control logic, and on-chip memories. The data path logic is primarily realized by using repeatable structured general purpose function blocks, while the control logic is designed using standard cells or programmable logic arrays (PLA's). A cell library and powerful CAD programs are utilized to shorten the TAT. A CMOS 16-bit micro-computer is designed with this approach and compared with a fully automated standard cell chip. A gate density improvement of 30 percent is observed. A design effort of only 20 man-months is achieved.

An integrated modular and standard cell VLSI design approach

An advanced design method integrating different design approaches is proposed which can attain an optimized chip design within an acceptable turnaround time (TAT). Logic VLSI networks can be generally partitioned into data path logic, control logic, and on-chip memories. The data path logic is primarily realized by using repeatable structured general purpose function blocks, while the control logic is designed using standard cells or programmable logic arrays (PLA's), A cell library and powerful CAD programs are utilized to shorten the TAT. A CMOS 16-bit micro-computer is designed with this approach and compared with a fully automated standard cell chip. A gate density improvement of 30 percent is observed. A design effort of only 20 man-months is achieved.