Transformations and resynthesis for testability of RT-level control-data path specifications

Abstract

In order to remain competitive,a company needs to reduce its product development time,and consequently the development time for prototyping has to be reduced as well.One way to decrease the development time of a product is to synthesize the design description automatically to FPGAs (Field Programmable Gate Arrays).This article describes the experience of implementing a real-time kernel in hardware using VHDL for behavioral and data flow (RTL) description, simulation,synthesis to gate level,back-annotation and programming FPGAs for a prototype.