Datapath Circuits Research Articles

A full bit prefetch architecture for synchronous DRAM's

A high performance data path circuit design for Synchronous DRAM's (SDRAM's) is described. Data lines by second-level of metal above memory cells achieve a low power and area efficient full bit prefetch capability. An experimental 3.3-V 16-Mb SDRAM is developed based on this architecture. Since the full burst read data are latched in I/O sense amplifiers by a single CAS access, a precharge operation can start as early as two clocks before the data burst cycles begin. The early precharge function allows next RAS and CAS accesses during burst reads of the previous data. With a burst length of eight, a seamless read operation is possible for any row addresses even within the same bank. The full bit prefetch architecture enables low active power data burst operations because high frequency clock driven circuits are limited to the data path only. The SDRAM with a 1M/spl times/16-b configuration dissipates a 65-mA active current at a 100-MHz full page mode operation.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Asynchronous datapaths and the design of an asynchronous adder

This article presents a general method for designing delay-insensitive datapath circuits. Its emphasis is on the formal derivation of a circuit from its specification. We discuss the properties required in a code that is used to transmit data asynchronously, and we introduce such a code. We introduce a general method (in the form of a theorem) for distributing the evaluation of a function over a number of concurrent cells. This method requires that the code be distributive. We apply the method to the familiar example of a ripple-carry adder, and we give a CMOS implementation of the adder.

Rapid prototyping of ASICs with OASIS

OASIS is a cell-based design system with four major components: the compiler and logic synthesizer, the simulator and verifier, the automatic test pattern generator, and the automatic layout generator. The design flow is top-down as illustrated in the chart below. Currently, the design is captured in LOGIC-III, a PASCAL-like programming language that combines both the functional and structural descriptions. The functional description specifies finite state machines and decoding logic that can be readily synthesized into circuit structures by way of logic synthesis. A scan-path can be inserted automatically in every synthesized component. Data-path circuits are synthesized hierarchically from parameterized structural/functional descriptions of subcomponents. Tools for redundancy identification can be used to detect and to remove any untestable logic.

Processor components: data path and control circuits

Processor components: data path and control circuits