Cylindrical Gate All Around Research Articles

Sensitivity enhancement using triple metal gate work function engineering of junctionless cylindrical gate all around SiNW MOSFET based biosensor for neutral biomolecule species detection for upcoming sub 14 nm technology node

In the present work Dielectric Modulation (DM) technique along with Triple Metal (TM) gate engineering has been used for the junctionless (JL) cylindrical gate all around (CGAA) Si nanowire (NW) MOSFET based biosensor for label free electrical detection of neutral biomolecules species like Uricase, Streptavidin, Protein, Biotin, ChOx (choline oxidase), and APTES etc. For this device, the Drift Diffusion approach has been used along with self-consistent solution of Schrodinger’s equation with Poisson’s equation. For the biomolecule immobilization, a nanogap cavity region is formed in the JL SiNW MOSFET by etching gate oxide layer above the SiO2 interfacial layer. The change in the drain current (ID), threshold voltage (Vth), off-current sensitivity (SIoff), threshold voltage sensitivity (SVth) and Ion/Ioff current ratio of the device have been considered as the sensing parameters for detection of biomolecules under dry environment condition. In present work a new sensing metric of sensing of biomolecules – DIBL has been added which has never been reported in literature. In this work for JL SiNW, sensitivity metrics like smaller DIBL ∼50.47 mV/V, higher SIoff9.33×105, higher SVth28.72, nearly ideal subthreshold slope (SS) ∼60 mV/dec, and higher Ion/Ioff current ratio ∼9.01 × 1012 have been obtained in comparison to available literature results.

Impact of interface traps and noise analysis on dual material graded channel CGAA FET: A device reliability

This paper explores the effects of changing the device's parameters, such as the gate length (Lg), nanowire radius (r), oxide thickness (tox), and frequency (f), on the noise characteristics of dual material graded channel (DMGC) cylindrical gate all around (CGAA) FET while considering the presence and absence of interface trap charges. The performance analysis of the DMGC CGAA FET with that of the SMGC (single material graded channel) CGAA FET, is carried out while taking into account the impact of trap charges. It's noteworthy that the DMGC FET demonstrates significant advantages, with improvement in Ion/Ioff, reduction in DIBL, and SS when compared to the SMGC CGAA FET, both in the cases of without and with traps. The investigation also extends to analyse the analog/RF performance of the DMGC FET, for different type of trap charges. Furthermore, the power spectral densities of current noise (Sid) and voltage noise (Svg) are examined by varying the device dimensions and temperature. This also addresses the various sources of noise, including flicker noise (1/f), generation-recombination (G-R) noise, and diffusion noise. These types of noise have different prevalence depending on the operating frequency. At low frequencies, flicker and G-R noises dominate, while at higher frequencies, diffusion noise becomes the prominent factor impacting the device's performance. The research findings indicate that the optimal performance of the DMGC CGAA FET is achieved with smaller nanowire radius and thinner oxide thickness, regardless of trap charges. These findings offer valuable insights for improving the design and performance of DMGC CGAA FET in low power applications.

Threshold voltage modeling based comparative performance exploration of Junctionless and Junction-Based High-K gate stack Dual-Material Cylindrical Gate-All-Around Macaroni MOSFET

This paper presents explicit threshold voltage modeling based comparative threshold voltage exploration of Junctionless (JL) and Junction-based (JB) High-K gate stack (HKGS) Dual-Material (DM) Cylindrical Gate-all-around (CGAA) Macaroni (Mac.) MOSFET. Based on Young’s popular Parabolic Potential Approximation (PPA), device features like inner potential has been formulated. Based on the expression of inner potential, threshold voltage has been extracted. Other major short channel effects like Drain-induced barrier lowering (DIBL) and subthreshold swing (SS) have also been analyzed. Device parameters such as inner, outer radii, channel lengths, type of high-k gate oxide, source/drain doping for JB device, etc. have also been varied to examine their effects on device parameters. Finally mathematical outputs have been corroborated with simulation outputs from Atlas.

Temperature Analysis of DMGC CGAA FET for Future Deep Space and Military Applications: An Insight into Analog/RF/Self-Heating/Linearity

This manuscript introduces a pioneering investigation on the temperature effects of Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET by outlining its significance in various aspects such as analog/RF, self-heating, and linearity performance metrics. For this analysis, we have proposed a DMGC CGAA FET by amalgamating the gate and channel engineering techniques and the temperature is varied from 250 K to 450 K. A significant improvement in Ion/Ioff, SS, and DIBL by an amount of 96.98%, 19.49%, and 51.26% is obtained respectively for the proposed DMGC CGAA FET as compared to the single material graded channel (SMGC) CGAA FET. As the temperature is reduced from 450 K to 250 K, a noticeable improvement in analog/RF figure of merits and delay is obtained. Further, the self-heating effect (SHE) analysis revealed that the utilization of lower Rth is preferrable to minimize SHE in the device. Moreover, linearity parameters like gm2, gm3, VIP2, VIP3, IIP3 and IMD3 are noticed to be better for lower temperatures at higher VGS indicating good linearity. The obtained results make proposed device an ideal choice for various applications especially that operate in low temperature environments such as deep space, military, and RF applications.

Circuit Level Analysis of a Dual Material Graded Channel (DMGC) Cylindrical Gate All Around (CGAA) FET at Nanoscale Regime

Gate-all around (GAA) device is one of the cutting-edge technologies in the present semiconductor era owing to enhanced gate controllability and scalability at the nanoscale regime. The advantages of available GAA devices can further be improved by incorporating the dual material (DM) and graded channel (GC) techniques. To make use of these advantages, this manuscript investigates for the first time, the performance analysis of DMGC cylindrical GAA (DMGC CGAA) FET and its circuit applications such as inverter, NAND, NOR, ring oscillator and 6T static random-access memory (SRAM). Through the analysis, it has been found that the Ioff, SS, DIBL, and Ion/Ioff ratio are enhanced by an amount of 96.93%, 19.49%, 51.26%, and 96.98% respectively for DMGC CGAA FET when compared to single metal graded channel (SMGC) CGAA FET. Single-k (SiO2) and dual-k (SiO2+HfO2) techniques are also utilized here to analyse the device performance and dual-k recorded better performance in comparison with single-k owing to reduced off-state currents. It is noticed that delay has been reduced greatly for Inverter, NAND, and NOR by an amount of 51.93%, 11.25%, and 10.07% respectively for dual-k when compared to single-k DMGC CGAA FET. The frequency of oscillations for Ring Oscillator is improved by 69.7% with dual-k than single-k. Further, the obtained results of SRAM are compared with the existing literatures and noticed that the proposed DMGC CGAA FET outperforms the other works making the device a potential candidature for high performance applications.

Diminish Short Channel Effects on Cylindrical GAA Hetero-gate Dielectric TFET using High-Density Delta

The examined work elucidates a novel concept on Gate All Around (GAA) hetero dielectric gate-cylindrical tunnel field-effect transistor (TFET) to reduce SCEs. In this paper, a hetero dielectric gate (HeG) integrated with Silicon-Germanium (Si-Ge) substrate material is proposed along with a novel placement of a high-density delta (HDD) layer across the source–channel junction to achieve high ION of 1.12 × 10−4 A/µm and robust IOFF of 9.7 × 10−17 A/µm at Vgs = 1.2 V with steepest subthreshold swing (SS) of 55 mV/decade. Designing and computation of the proffered structure have been done with the computer-aided design (TCAD) 3D device computation software. The systematic investigation in terms of AC and DC parameters, such as ON-current, OFF-current, Miller Capacitances (Gate-Drain Capacitance (Cgd)) and Gate-Source Capacitance (Cgs), are examined. Hetero-gate dielectric Cyl-TFET with high-density delta (HDD) is superior to other conventional structures. The result outcomes included a trap analysis while incorporating the hot charge carriers inside the oxide for improved device reliability. Furthermore, a low Cgd of 58fF and high Cgs of 6.6fF at Vds = 0.3 V have been achieved.

Threshold voltage modeling of Gaussian-doped Dual work function Material Cylindrical Gate-all-around (CGAA) MOSFET considering the effect of temperature and fixed interface trapped charges

Current research endeavor encompasses comprehensive threshold voltage analysis of a Gaussian-doped Dual work function Material (DM) Cylindrical Gate-all-around (CGAA) MOSFET with temperature variance in presence of fixed interface trap charges. Threshold voltage reliability over a wide range of temperature in presence of trap charges and its Gaussian-parameters such as projected range and straggle based dependencies are exhibited. Short channel response of the device has also been considered. Analytical results are corroborated through simulation outputs from Atlas.

Numerical Analysis of Gate-All-Around HfO2/TiO2/HfO2 High-K Dielectric Based WSe2 NCFET With Reduced Sub-Threshold Swing and High On/Off Ratio

Gate-all-around (GAA) field effect transistors (FETs) have appeared as one of the potential candidates for the electrostatic integrity required to reduce MOSFETs to minimum channel lengths. Meanwhile, the negative capacitance effect of ferroelectrics is known as a remarkable quality enhancer for MOSFETs in terms of reducing sub-threshold slope (SS), supply voltage, and power consumption by utilizing the gate voltage amplification phenomenon. In this work, combining these two phenomena we numerically design a cylindrical GAA NCFET where promising two-dimensional WSe2 is used as a channel material. We have suggested a high-K dielectric consisting of a tri-layer HfO2/TiO2/HfO2 and lead zirconate titanate (PZT) as a ferroelectric layer in the gate stacking. The extremely high $I_{on}/I_{off}$ ratio on the order of 1012 (six order higher than conventional FET), and the high on-state current of $119~\mu \text{A}$ are the most remarkable findings of this device which exceeds all the earlier results. The integration of the NC effect utilizing a 20 nm PZT offers lowest $SS$ of 18.9 mV/dec. Moreover, a large transconductance ( $g_{m}$ ) of $117~\mu \text{S}$ and a higher current cut-off frequency ( $f_{T}$ ) of 335 GHz were reported from the output characteristics. These outcomes allude that the suggested device structure may create a new path for electronic devices; therefore, it can be used for high speed operation with low power consumption.

Dual Material Gate Engineering to Reduce DIBL in Cylindrical Gate All Around Si Nanowire MOSFET for 7-nm Gate Length

In this work, drain current ID for 7-nm gate length dual-material (DM) cylindrical gate all around (CGAA) silicon nanowire (SiNW) has been studied and simulation results are reported using Silvaco ATLAS 3D TCAD. In this device, we consider the non-equilibrium Green’s function (NEGF) approach and self-consistent solution of Schrodinger's equation with Poisson’s equation. The splitting of conduction in multiple sub-bands has been considered and there is no doping in the channel region. The effect of DM gate engineering (variation of screen gate and control gate length having different work function) for SiNW channel with 2-nm radius and gate oxide (SiO2) thickness of 0.8 nm on ID have been studied. It was found that DM gate engineering reduces drain-induced barrier lowering (DIBL) but it also slightly increases sub-threshold slope (SS). This work has obtained small DIBL (~54 mV/V), small SS (~68 mV/dec), and higher IOn/IOff (~4 × 108) ratio as compared to literature concerning the inversion mode devices. The smallest DIBL is obtained when control gate length is the highest, and vice versa. With increase in control gate length, there is also increase in both IOn and IOff but IOn/IOff ratio decreases.

Design and Analog Performance Analysis of Charge-Plasma Based Cylindrical GAA Silicon Nanowire Tunnel Field Effect Transistor

Due to the rigorous practice of scaling down the device technology, certain factors such as proper electrostatic controlling of the channel, dopingless substrate, and low thermal budget at the nanoscale are the keys to designing better, efficient and cost-effective semiconductor devices. In this paper, a Charge-Plasma (CP) based Gate-All-Around (GAA) Silicon Nanowire Tunnel Field Effect Transistor (NWTFET) is proposed. Charge-Plasma technique is used to induce electron and hole concentration within the drain/source regions respectively by depositing layers of metals with specific work functions. The RF and analog performance of Dopingless Gate-All-Around Silicon Nanowire Tunnel Field Effect Transistor (DL-GAA-NWTFET) are investigated and compared with Junctionless Gate-All-Around Silicon Nanowire Tunnel Field Effect Transistor (JL-GAA-NWTFET) and Conventional Gate-All-Around Silicon Nanowire Tunnel Field Effect Transistor (C-GAA-NWTFET). The RF/Analog performance parameters such as Unity Gain Frequency (fT), Total Gate Capacitance (Cgg), Intrinsic Gain (Av), Early Voltage (VEA), Output Transconductance (gds), Transconductance to Gain Factor (TGF) and Transconductance (gm) are analyzed, which shows the enhanced output characteristics of the DL-GAA-NWTFET compared to JL-GAA-NWTFET and C-GAA-NWTFET. DL-GAA-NWTFET also provides two-order high ON-state current to the OFF-state current ratio (ION/IOFF) with an enhancement of the other sensing parameters.

Performance Assessment of the Charge-Plasma-Based Cylindrical GAA Vertical Nanowire TFET With Impact of Interface Trap Charges

In this article, a charge-plasma (CP)-based gate-all-around (GAA) silicon vertical nanowire tunnel field-effect transistor (NWTFET) is proposed. The effects of interface trap charges (ITCs) on dopingless (DL) NW-based device have been addressed for the first time. CP technique is used to induce charge carriers within the drain/source regions by depositing layers of metals with specific work function. Linearity performance parameters such as higher order harmonic distortions (HDs), intermodulation distortions (IMDs), and interception points are calculated including the effects of ITCs on the cylindrical channel-surround gate-oxide interface. This work shows that positive ITCs can help in improving the device characteristics, whereas negative ITCs degrade the device performance. The ON-state current to OFF-state current ratio decreases for either polarity of ITCs. The ON-state current has been improved by approximately 50% with higher positive ITCs. The presence of positive ITCs in DL NWTFET improves the driving capability to be used for analog applications. The linearity parameters tend to improve with positive ITCs and degrade with negative ITCs. The proposed device has reached the same cutoff frequency at lower operating gate bias (approximately 0.8 V) with half the threshold voltage for higher positive ITCs.

Cylindrical gate all around Schottky barrier MOSFET with insulated shallow extensions at source/drain for removal of ambipolarity: a novel approach

In this paper TCAD-based simulation of a novel insulated shallow extension (ISE) cylindrical gate all around (CGAA) Schottky barrier (SB) MOSFET has been reported, to eliminate the suicidal ambipolar behavior (bias-dependent OFF state leakage current) of conventional SB-CGAA MOSFET by blocking the metal-induced gap states as well as unwanted charge sharing between source/channel and drain/channel regions. This novel structure offers low barrier height at the source and offers high ON-state current. The ION/IOFF of ISE-CGAA-SB-MOSFET increases by 1177 times and offers steeper subthreshold slope (~60 mV/decade). However a little reduction in peak cut off frequency is observed and to further improve the cut-off frequency dual metal gate architecture has been employed and a comparative assessment of single metal gate, dual metal gate, single metal gate with ISE, and dual metal gate with ISE has been presented. The improved performance of Schottky barrier CGAA MOSFET by the incorporation of ISE makes it an attractive candidate for CMOS digital circuit design. The numerical simulation is performed using the ATLAS-3D device simulator.

Ambipolarity reduction in DMG asymmetric vacuum dielectric Schottky Barrier GAA MOSFET to improve hot carrier reliability

An explicit surface potential and subthreshold current model for novel Dual Metal Gate (DMG) Asymmetric Vacuum (AV) as gate dielectric Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with the incorporation of localized charges (Nf) is developed to provide excellent immunity against threshold voltage (Vth) degradation due to hot carriers. Hot carrier induced Localized Charges (LC) either positive or negative leads to degrade the threshold of the device. The major advantage of the proposed DMG-AV-SB-CGAA MOSFET is that it mitigates the ambipolar behavior thus offering very good on current to off current ratio; and also reduces the electron temperature which leads to less hot carrier generation thus lesser degradation in Vth and improved Hot Carrier reliability.The surface potential is determined for three different regions by solving 1-D Poisson’s and 2-D Laplace equation through separation of variable method to facilitate an optimal model for calculating the subthreshold drain current from Si-SiO2 interface boundary. The developed model results are in good agreement with that of ATLAS-TCAD simulation.

Gate-Induced Drain Leakage Reduction in Cylindrical Dual-Metal Hetero-Dielectric Gate All Around MOSFET

In this paper, an analytical model of dual-metal hetero-dielectric (DM-HD) cylindrical gate all around (GAA) MOSFET has been proposed to address and solve a substantial issue of gate-induced drain leakage (GIDL) current in order to improve the device reliability, band-to-band tunneling (BTBT), and OFF state leakages. The structure is based upon asymmetric gate oxide structure by combining silicon dioxide (SiO2) gate dielectric at source side and vacuum dielectric at drain side, which significantly reduces BTBT and OFF-state gate leakages, thereby making it suitable for low-power applications. It is examined that GIDL i.e., an OFF-state leakage phenomenon, is reduced in DM-HD GAA MOSFET by lowering the BTBT. This can be done by reducing OFF-state leakages due to: 1) increase in tunneling width and 2) increased barrier height from source to channel. The results show that the OFF-state leakage current in DM-HD GAA MOSFET reduces to an order of $10^{-\textsf {13}}$ over $10^{-\textsf {9}}$ A as in the case of conventional GAA MOSFET. The results so obtained are compared with those of cylindrical dual-metal GAA (DM-GAA) MOSFET and GAA MOSFET to analyze its performance. OFF-state leakages at higher temperatures have also been analyzed.

Analog and RF performance of a multigate FinFET at nano scale

In this paper, analog and RF performance of the Fin field effect transistor (FET) at Nano scale is observed through 3D simulation. FinFET devices like rectangular gate all around (RE-GAA) FinFET, cylindrical gate all around (CY-GAA) FinFET and triple gate (TG) FinFET are observed. The figure of merit (FOMs) such as input-output characteristics, trans-conductance (gm), output-conductance (gd), intrinsic gain (gm/gd), gate capacitance (gate to source and total gate capacitance), unity gain cut-off frequency (ft), trans-conductance generation factor (TGF), gain frequency product (GFP), gain bandwidth product (GBP) and gain transconductance frequency product (GTFP) are observed. The analog performance of a FinFETs are observed by realising source follower circuit with NMOS transistor as a current source. The source follower circuit gain is observed. It has been observed that maximum capacitance is observed in case gate all around condition. Rectangular gate all around has the highest transconductance. In the source follower circuit, the gain curve (Vout/Vin) is sharper for TG-FinFET.

Analytical model of threshold voltage degradation due to localized charges in gate material engineered Schottky barrier cylindrical GAA MOSFETs

The threshold voltage degradation due to the hot carrier induced localized charges (LC) is a major reliability concern for nanoscale Schottky barrier (SB) cylindrical gate all around (GAA) metal–oxide–semiconductor field-effect transistors (MOSFETs). The degradation physics of gate material engineered (GME)-SB-GAA MOSFETs due to LC is still unexplored. An explicit threshold voltage degradation model for GME-SB-GAA-MOSFETs with the incorporation of localized charges (Nit) is developed. To accurately model the threshold voltage the minimum channel carrier density has been taken into account. The model renders how +/− LC affects the device subthreshold performance. One-dimensional (1D) Poisson’s and 2D Laplace equations have been solved for two different regions (fresh and damaged) with two different gate metal work-functions. LCs are considered at the drain side with low gate metal work-function as Nit is more vulnerable towards the drain. For the reduction of carrier mobility degradation, a lightly doped channel has been considered. The proposed model also includes the effect of barrier height lowering at the metal–semiconductor interface. The developed model results have been verified using numerical simulation data obtained by the ATLAS-3D device simulator and excellent agreement is observed between analytical and simulation results.

Performance enhancement of asymmetrical underlap 3D‐cylindrical GAA‐TFET with low spacer width

A comparative study of cylindrical gate-all-around (Cyl-GAA) tunnel field effect transistor (TFET) based on underlaps with varying spacer width is presented. Extensively, simulation results show that asymmetrical underlap (AU) GAA-TFET with low spacer width enhances the fringing field within the spacer. The proposed device structure has high I ON (6.9 × 10−4 A/µm), low I OFF (2.5 × 10−17 A/µm), and an enhanced I ON/I OFF (1013). This is due to the high series resistance at drain channel junction caused by AU. Furthermore, the proposed structure exhibits a steeper subthreshold swing (30 mV/dec) when compared with symmetrical underlap (SU) Cyl-GAA-TFET.

DS Schottky barrier cylindrical GAA MOSFET: nanosensor for biochips

This paper presents an extensive mathematical study of a proposed nanogap-embedded dopant-segregated (DS) Schottky barrier (SB) cylindrical gate all-around (CGAA) metal-oxide-semiconductor field-effect transistor (MOSFET) of negatively/positively charged and neutral species observed by numerical simulation using an Atlas three-dimensional device simulator for electrical and label-free detection of bio/chemical (DNA, pH) and neutral species (protein) respectively as a nanosensor in the biomedical field at high sensitivity for direct electronic readout. This is the first time that the use of a nanogap-embedded DS-SB-CGAA MOSFET as a bio/chemical sensor has been reported. The threshold voltage (V th) shift and change in current are considered as sensing metrics to detect biological or chemical species when they are immobilized in the carvel-built region. The shift in on current (I on) of the nanogap-embedded DS-SB-CGAA MOSFET is also taken as a sensing metric, and better performance is observed compared to a conventional SB-CGAA MOSFET sensor. It is advantageous in terms of its low power/energy consumption as well as from the point of view of integration with the forthcoming silicon-based lab-on-chip systems due to the compatibility with the complementary metal-oxide semiconductor process.

Physics based analytical model for surface potential and subthreshold current of cylindrical Schottky Barrier gate all around MOSFET with high-k gate stack

A physics-based analytical model for Schottky Barrier (SB) Cylindrical Gate All Around (CGAA) MOSFET with high-k dielectric is presented with Evanescent Mode Analysis (EMA). The electrostatic potential is obtained using the Superposition method. An exact expression for threshold voltage and subthreshold slope is also obtained. The proposed model also includes the effect of Barrier height lowering at metal semiconductor interface along with the effect of high-k (HfO2) gate stack. Diffusion current and tunneling currents are combined to evaluate the total subthreshold current. The analytical results so obtained are compared with simulated data and they are in good agreement. The proposed model of SB-CGAA device with high-k dielectric is very useful for the design and optimization for high current and improved performance.

Analytical modeling of threshold voltage for Cylindrical Gate All Around (CGAA) MOSFET using center potential

Abstract In this paper, an analytical threshold voltage model is proposed for a cylindrical gate-all-around (CGAA) MOSFET by solving the 2-D Poisson’s equation in the cylindrical coordinate system. A comparison is made for both the center and the surface potential model of CGAA MOSFET. This paper claims that the calculation of threshold voltage using center potential is more accurate rather than the calculation from surface potential. The effects of the device parameters like the drain bias ( V DS ) , oxide thickness ( t ox ) , channel thickness (r), etc., on the threshold voltage are also studied in this paper. The model is verified with 3D numerical device simulator Sentaurus from Synopsys Inc.