Cylindrical Gate All Around Research Articles

Investigation on cylindrical gate all around (GAA) to nanowire MOSFET for circuit application

Undoped cylindrical gate all around (GAA) MOSFET is a radical invention and a potential candidate to replace conventional MOSFET, as it introduces new direction for transistor scaling. In this work, the sensitivity of process parameters like channel length ( L g), channel thickness ( t Si ), and gate work function ( φ M ) on various performance metrics of an undoped cylindrical GAA to nanowire MOSFET are systematically analyzed. The electrical characteristics such as on current ( I on ), subthreshold leakage current ( I off ), threshold voltage ( V th ) and similarly analog/RF performances like transconductance ( g m ), total gate capacitance ( C gg ), and cut-off frequency ( f T ) are evaluated and studied with the variation of device design parameters. The discussion give direction towards low standby operating power (LSTP) devices as improvement in I off is approaching 90% in nanowire MOSFET. All the device performances of undoped GAA MOSFET are investigated through Sentaurus device simulator from Synopsis Inc.

Novel 4<italic>F</italic><sup>2</sup> Buried-Source-Line STT MRAM Cell With Vertical GAA Transistor as Select Device

Spin transfer torque (STT) magnetic random access memories (MRAMs) have recently emerged as one of the strongest contenders for universal memory technology. They have entire range of features, i.e., high speed, nonvolatility, high density, and low power, which make them cynosure to every memory designer's notion. Researchers are working ardently to use STT MRAMs under continuously increasing scaling challenges. To accommodate a larger amount of embedded memory, the cell size must be reduced. Therefore, the designs target to attain an optimistic figure of 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> (F being the feature size) array density, which is the maximum achievable two-dimensional (2-D) density. With this objective in mind, a novel 4F <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> buried-source-line (SL) STT MRAM cell structure with a vertical gate all around (GAA) cylindrical buried source NMOS transistor is proposed. The magnetic tunnel junction (MTJ) multilayer structure is stacked above the select device with both occupying the same 2-D area. The diameters of perpendicular MTJ and vertical silicon nanowire are equal (i.e., F). Device simulations have been carried out on TCAD for buried source vertical GAA device structure. Furthermore, these TCAD results are used to calibrate the BSIM CG model for cylindrical GAA transistors. The proposed STT MRAM cell is then analyzed using calibrated Verilog-A models for perpendicular anisotropy MTJ and vertical GAA NMOS transistor (BSIM CG). The performance analysis in terms of read stability, write margins, and power dissipation for the proposed cell is also presented.

An analytical subthreshold current modeling of cylindrical gate all around (CGAA) MOSFET incorporating the influence of device design engineering

An analytical model of CGAA MOSFET incorporating material engineering, channel engineering and stack engineering has been proposed and verified using ATLAS 3D device simulator. A comparative study of short channel effects for various device structures has also been carried out incorporating the effect of drain induced barrier lowering (DIBL), threshold voltage lowering and degradation of subthreshold slope. The effectiveness of applying the three region doping profile concept in the channel such as high-medium-low and low-high-low and its comparison with Gaussian doping profile to the cylindrical GAA MOSFET has been examined in detail. Reduced SCEs have been evaluated in combined designs i.e. TM–GC–GS, GCGS and DM–GC–GS. Out of several design engineering, GC–GS CGAA gives nearly ideal subthreshold slope whereas TM–GC–GS CGAA provides overall superior performance to reduce SCEs in deep nano-meter. The results so obtained are in good agreement with the simulated data which validate the model.

Gate-All-Around Nanowire MOSFET With Catalytic Metal Gate For Gas Sensing Applications

In this paper, gate-all-around (GAA) MOSFET with catalytic metal gate is proposed for enhanced sensitivity of gas sensor. P-channel GAA MOSFET with palladium (Pd) metal gate is used for hydrogen sensing and n-channel GAA MOSFET with silver (Ag) metal gate is used for Oxygen sensing. The GAA nanowire MOSFET has already been demonstrated experimentally for biosensing and chemical sensing applications. However, cylindrical GAA MOSFET with catalytic metal gate for gas sensing applications is proposed for the first time in this paper. An analytical model is developed for both p-channel and n-channel GAA MOSFET to calculate the sensitivity of the device in the presence of gas molecules and analytical model is verified with the simulation results of ATLAS-3D. Sensitivity of the GAA MOSFET gas sensor is compared with the conventional bulk MOSFET gas sensor and impact of the radius of the silicon pillar on the sensitivity of the GAA MOSFET is also studied.

A Universal Core Model for Multiple-Gate Field-Effect Transistors. Part II: Drain Current Model

A universal drain current model for multiple-gate field-effect transistors (FETs) (Mug-FETs) is proposed. In Part I, a universal charge model was derived using the arbitrary potential method. Using this charge model, Pao-Sah's integral is analytically carried out by approximating its integrand. The model describes both the subthreshold inversion for undoped FETs and the effects of finite doping density in the channel. With an explicit and continuous expression, the proposed drain current model covers all regions of device operation: subthreshold, linear, and saturation. The accuracy from the proposed model is comparable with that from well-known previous models for double-gate (DG) and cylindrical gate-all-around (Cy-GAA) FETs with an undoped channel. In addition, the model shows good agreement with 2-D and 3-D numerical simulations for doped-channel multiple-gate structures such as single-gate, DG, triple-gate, rectangular gate-all-around, and Cy-GAA FETs. The proposed model is well suited to be a core model for Mug-FETs due to its good computational efficiency and high accuracy; hence, it is useful for compact modeling.

Precise Modeling Framework for Short-Channel Double-Gate and Gate-All-Around MOSFETs

A precise modeling framework for short-channel nanoscale double-gate (DG) and gate-all-around (GAA) MOSFETs is presented. For the DG MOSFET, the modeling is based on a conformal mapping analysis of the potential distribution in the device body arising from the interelectrode capacitive coupling, combined with a self-consistent procedure to include the effects of the inversion charge. The DG interelectrode coupling, which dominates the subthreshold behavior of the device, can also be applied with a high degree of precision to the cylindrical GAA MOSFET by performing a simple geometric scaling transformation to account for the difference in gate control in the two devices. Near threshold, self-consistent procedures invoking Poisson's equation in combination with boundary conditions and suitable modeling expressions for the potential are applied to the two devices. In strong inversion, these solutions converge to those of the respective long-channel devices. The drain current is calculated as part of the self-consistent treatment. The results for both the electrostatics and the current are in excellent agreement with numerical simulations.