Custom VLSI Research Articles

A biologically inspired modular VLSI system for visual measurement of self-motion

We introduce a biologically inspired computational architecture for small-field detection and wide-field spatial integration of visual motion based on the general organizing principles of visual motion processing common to organisms from insects to primates. This highly parallel architecture begins with two-dimensional (2-D) image transduction and signal conditioning, performs small-field motion detection with a number of parallel motion arrays, and then spatially integrates the small-field motion units to synthesize units sensitive to complex wide-field patterns of visual motion. We present a theoretical analysis demonstrating the architecture's potential in discrimination of wide-field motion patterns such as those which might be generated by self-motion. A custom VLSI hardware implementation of this architecture is also described, incorporating both analog and digital circuitry. The individual custom VLSI elements are analyzed and characterized, and system-level test results demonstrate the ability of the system to selectively respond to certain motion patterns, such as those that might be encountered in self-motion, at the exclusion of others.

KPIX: a pixel detector imaging chip

We present a VLSI custom device, named KPIX, developed in a 0.6 μm CMOS technology. The circuit is dedicated to readout solid-state detectors covering large areas (on the order of square centimetre) and featuring very small currents. KPIX integrates 1024 channels (current amplifiers) and 8 ADCs on a 15.5×4 mm 2 area. Both an analogue and digital readout are allowed, with a 10 bit amplitude resolution. Amplifiers are organized in 8 columns of 128 rows. When choosing the digital or the analogue readout, the complete set of channels can be read out in about 30 ms. The specific design of the amplification cells allows to measure very small input current levels, on the order of fractions of pico-ampere. Power consumption has also been kept at the level of 80 μW per cell and 150 mW (peak value) in total. The specific chip architecture and geometry allow use of many KPIX circuits together in order to serve a large detector sensitive area. The KPIX structure is presented along with some measurements characterizing its performance.

A high granularity imaging calorimeter for cosmic-ray physics

An imaging calorimeter has been designed and is being built for the PAMELA satellite-borne experiment. The physics goals of the experiment are the measurement of the flux of antiprotons, positrons and light isotopes in the cosmic radiation. The calorimeter is designed to perform a precise measurement of the total energy deposited, to reconstruct the spatial development of the showers (both in the longitudinal and in the transverse directions), and to measure the energy distribution along the shower itself. From this information, the calorimeter will identify antiprotons from an electron background and positrons in a background of protons with an efficiency of about 95% and a rejection power better than 10 −4. Furthermore, a self-trigger system has been implemented with the calorimeter that will be employed to measure high-energy (from about 300 GeV to more than 1 TeV) electrons. The instrument is composed of 22 layers of tungsten, each sandwiched between two “views” of silicon strip detectors ( X and Y). The signals are read out by a custom VLSI front-end chip, the CR1.4P, specifically designed for the PAMELA calorimeter, with a dynamic range of 7.14 pC or 1400 minimum ionizing particle (mip). We report on the simulated performance and prototype design.

Space-Time Equations for Non-Unimodular Mappings

The class of systems of uniform recurrence equations (UREs) is closed under uni-modular transformations. As a result, every systolic array described by a unimodular mapping can be specified by a system of space-time UREs, in which the time and space coordinates are made explicit. As non-unimodular mappings are frequently used in systolic designs, this paper presents a method that derives space-time equations for systolic arrays described by non-unimodular mappings. The space-time equations for non-unimodular mappings are known elsewhere as sparse UREs (SUREs) because the domains of their variables are sparse and their data dependences are uniform. Our method is compositional in that space-time SUREs can be further transformed by unimodular and non-unimodular mappings, allowing a straightforward implementation in systems like ALPHA. Specifying a systolic design by space-time equations has two advantages. First, the space-time equations exhibit all useful properties about the design, allowing the design to be formally verified. Second, depending on the application area and performance requirement, the space-time equations can be realised as custom VLSI systems, FPGAs, or programs to be run on a parallel computer.

Image-sequence motion estimation for the Dervish mine-clearance vehicle

The paper reports on the application of block matching with spatial transforms to image sequences of ground scenes taken from a moving camera. The motion is a general combination of rotation and translation. The use of spatial transforms with interpolation filtering to generate rotation reference templates and the hardware implementation, for use on a robot mine-clearance vehicle, are novel. It is shown that the emerging generation of single chip floating-point digital signal processors and CMOS image sensors are well suited to rapid prototyping of image sequence analysis, which has previously been the domain of expensive camera and custom VLSI hardware or cumbersome parallel machines.

Multitier Wireless Communications

Next-generation computing systems will be highly integrated using wireless networking. The Rice Everywhere NEtwork (RENE) project is exploring the integration of WCDMA cellular systems, high speed wireless LANs, and home wireless networks to produce a seamless multitier network interface. We are currently developing a simulation acceleration testbed and a multitier network interface card (mNIC) consisting of DSP processors, custom VLSI ASICs, and FPGAs for baseband signal processing to interact with the various RF units and the host processor. This testbed will also allow us to explore high performance algorithm alternatives through computer aided design tools for rapid prototyping and hardware/software co-design of embedded systems.

A Parallel Architecture for the 2-D Discrete Wavelet Transform with Integer Lifting Scheme

In this paper we propose a dedicated architecture to implement a 2-D discrete wavelet transform computed by adopting the new lifting scheme framework. Through this new construction tool it is possible to obtain integer versions of the wavelet transform. This is a very interesting issue when the goal is lossless compression of images, whose pixels are represented through integers. In the classical approach to the discrete wavelet, the filter coefficients are real numbers and so are the resulting coefficients. When pursuing hardware implementations for real time and embedded applications, this causes the need to manage fixed point operations and unavoidable quantization. If the output can be produced with integer values instead, perfect reconstruction and lossless compression are possible. Typical applications include scenarios with limited bandwidth and big image sizes, such as medical imaging for tele-medicine or satellite image transmission, not suited to lossy compression, or high quality images in digital cameras. We analyze the data flow and dependencies to define an architecture to implement the integer lifting wavelet transform. The paper covers all lifting implementations based on a single ‘lifting stepr’ and uses the Deslauriers-Dubuc (4, 2) filter as a guiding example, but the approach is general and the results can be easily extended to other filters. We outline a very general framework, to be used either in a custom VLSI implementation, or in mappings onto existing ‘computing cells’. The overall resources needed are less than those for the equivalent classical FIR version computed through a systolic architecture.

Application of Reconfigurable Computing to a High Performance Front-End Radar Signal Processor

Many radar sensor systems demand high performance front-end signal processing. The high processing throughput is driven by the fast analog-to-digital conversion sampling rate, the large number of sensor channels, and stringent requirements on the filter design leading to a large number of filter taps. The computational demands range from tens to hundreds of billion operations per second (GOPS). Fortunately, this processing is very regular, highly parallel, and well suited to VLSI hardware. We recently fielded a system consisting of 100 GOPS designed using custom VLSI chips. The system can adapt to different filter coefficients as a function of changes in the transmitted radar pulse. Although the computation is performed on custom VLSI chips, there are important reasons to attempt to solve this problem using adaptive computing devices. As feature size shrinks and field programmable gate arrays become more capable, the same filtering operation will be feasible using reconfigurable electronics. In this paper we describe the hardware architecture of this high performance radar signal processor, technology trends in reconfigurable computing, and present an alternate implementation using emerging reconfigurable technologies. We investigate the suitability of a Xilinx Virtex chip (XCV1000) to this application. Results of simulating and implementing the application on the Xilinx chip is also discussed.

High resolution CdZnTe pixel detectors with VLSI readout

CdZnTe pixel detectors with a custom VLSI readout, are being developed at Caltech/JPL for use in focusing hard X-ray telescopes. We have recently tested several prototype detector assemblies, each consisting of a 2 mm thick CdZnTe pixel detector indium bump bonded to our VLSI readout chip. A complete pulse height analysis chain is located directly below each 680 by 650 /spl mu/m pixel and includes a preamplifier, shaping amplifiers, and a peak stretcher/discriminator. Here we report on the first fully functional operation of these detector/VLSI hybrids. Using an /sup 241/Am source, collimated to illuminate a single pixel, excellent energy resolution of 670 eV FWHM was measured for the 59.5 keV line at -10 C, with electronic noise of only 340 eV FWHM. Illumination with an uncollimated /sup 241/Am source was performed to assess the uniformity of pixel response and to exercise the readout chip's ability to process multiple pixel events arising from X-rays interacting above pixel boundaries. The imaging capability of the detector was demonstrated using a tungsten slit mask.

Data read out and formatting for PMT-based rich detectors

A compact Data Read Out System has been developed for PMT-Based Rich to perform the charge conversion, pixel encoding and data formatting for a large number of channels. This system is principally built around three circuits: A full custom VLSI circuit (ASIC) for charge conversion, a Field Programmable Gate Array (FPGA) for pixel encoding, thresholds and 12-bit ADC control, and a fast Digital Signal Processor (DSP) for data formatting.

A VLSI chip set for digital radiology with energy selection

We present a compact acquisition system for digital radiology, based on GaAs detectors. The system is based on a custom VLSI circuit set, with analog and digital functions for the acquisition of radiological images in a wide range of applications. The circuit architectures and the operating principles are presented. We use a broad spectrum X-ray tube and try to exploit the full physical information contained in the incident radiation by means of both single photon counting and energy measurement of each photon.

Data acquisition system for E-835 silicon detector

In this paper we describe the DAQ system for the silicon pad detector used in experiment E-835 at Fermilab. It is composed of three different electronic boards that perform detector read-out, zero suppression and store data in a VME memory segment. The system is based on high performance VLSI custom components for data encoding and zero suppression to achieve the maximum reliability and performance. Furthermore, all logic functions have been implemented using FPGAs to handle the second level trigger. The whole system has been fully tested at CERN in November 1995 and installed at Fermilab in September 1996.

Description and demonstration of a CMOS amplifier-based-system with measurement and stimulation capability for bioelectrical signal transduction

An extracellular recording system incorporating an electrode array and an amplifier/stimulator CMOS chip is described and characterized. Important features of this custom VLSI chip include 16 instrumentation amplifiers with a gain of 50 and the incorporation of a cross-point array allowing designation of an extracellular microelectrode as either a stimulator or sensor. The planar array consisted of 32 microelectrodes, 14 μm in diameter, and four larger reference electrodes. Microelectrodes, interconnecting traces, and bond pads were patterned with a 500-nm layer of gold. The interconnecting traces were passivated with a 1-μm thick layer of silicon nitride to provide chemical and electrical insulation and microelectrode impedance was lowered utilizing electrode position of platinum black. The amplifier exhibited a nearly flat frequency response with high pass and low pass corner frequencies of 0.7 Hz and 50 kHz, respectively. The input referred noise over the 50 kHz bandwidth was 12–16 μV RMS, well below the magnitude of previously reported extracellular potentials. Crosstalk between neighboring channels resulted in an output signal below the amplifier noise level, even for relatively large extracellular potentials. Using this system, extracellular recordings were demonstrated yielding typical peak-to-peak biopotentials of magnitude 0.9–2.1 mV and 100–400 μV for chick cardiac myocytes and rat spinal cord neurons, respectively. The key components of this extracellular recording system can be manufactured using industry standard thin film photolithographic techniques.

An agile ISM band frequency synthesizer with built-in GMSK data modulation

In this paper, a high-resolution fractional-N RF frequency synthesizer is presented which is controlled by a fourth-order digital sigma-delta modulator. The high resolution allows the synthesizer to be digitally modulated directly at RF. A simplified digital filter which makes use of sigma-delta quantized tap coefficients is included which provides built-in GMSK pulse shaping for data transmission. Quantization of the tap coefficients to single-bit values not only simplifies the filter architecture, but the fourth-order digital sigma-delta modulator as well. The synthesizer makes extensive use of custom VLSI, with only a simple off-chip loop filter and VCO required. The synthesizer operates from a single 3-V supply, and has low power consumption. Phase noise levels are less than -90 dBc/Hz at frequency offsets within the loop bandwidth. Spurious components are less than -90 dBc/Hz over a 19.6-MHz tuning range.

Design and Implementation of the PAPRICA Parallel Architecture

In this paper PAPRICA, a massively parallel coprocessor devoted to the analysis of bitmapped images is presented considering first the computational model, then the architecture and its implementation, and finally the performance analysis. The main goal of the project was to develop a subsystem to be attached to a standard workstation and to operate as a specialized processing module in dedicated systems. The computational model is strongly related to the concepts of mathematical morphology, and therefore the instruction set of the processing units implements basic morphological transformations. Moreover, the specific processor virtualization mechanism allows to handle and process multiresolution data sets. The actual implementation consists of a mesh of 256 single bit processing units operating in a SIMD style and is based on a set of custom VLSI circuits. The architecture comprises specific hardware extensions that significantly improved performances in real-time applications.

The digital mammography program at the SR light source in Trieste

A synchrotron radiation beamline devoted to medical imaging has been built by the SYRMEP collaboration at Elettra in Trieste, Italy, and is now in operation. The SYRMEP imaging system is based on the combination of a monochromatic, laminar X-ray beam, with a laminar, high-efficiency pixel silicon detector. To image soft tissue, including small, low-contrast details, as in mammography, beam energies should be chosen in the range from 15 keV to 30 keV and the detector should be capable of single-photon counting. The SYRMEP beamline originates from a bending magnet light port and consists basically of a Be window, a slit system and a Si(1,1,1) crystal monochromator. The experimental area is equipped with a radiation flux monitor, a sample movement stage, and a positioning system holding the silicon detector. Images are obtained by keeping the detector stationary with respect to the beam and by scanning the sample through the beam itself. The current detector is a linear array of 200/spl times/300 /spl mu/m/sup 2/ pixels, each coupled to its electronic counting chain on a custom VLSI read-out chip. We present a summary of beam studies, and digital images of standard RMI 160 and RMI 180 Ackermann Mammographic phantoms. Results show the high contrast resolution, the good spatial resolution and the large dynamic range which constitute the defining characteristics of the SYRMEP imaging system.

A reconfigurable VLSI coprocessing system for the block matching algorithm

Several VLSI architectures for the full-search block matching algorithm have been proposed in recent years due to its computation and I/O-intensive nature and its importance in various computer vision and image processing applications. This paper presents a new coarse grained reconfigurable coprocessor which is suitable for integration with general purpose microprocessors. The 180000 transistor custom VLSI design was implemented in 0.6 /spl mu/m CMOS on a 4.12 min/spl times/2.59 mm die and has been fully tested up to 33 MHz. For a typical image database search application, a sample system consisting of four coprocessors interfaced through a 33 MHz PCI bus will provide a speedup of 320/spl times/ over an 80486 DX2/66 MHz and 64/spl times/ over a 150-MHz Pentium running fully optimized assembly code.

A commandable pulse height analysis system based on custom VLSI ASICs for the Cassini space mission

The authors have implemented a new commandable threshold PHA-accumulation unit for the MIMI/LEMMS particle detection instrument of the Cassini mission to Saturn. The implementation is based on two full custom VLS ASICs specifically designed, fabricated, and space qualified for this project. The present system overcomes common fine tuning pre-flight and in-flight calibration difficulties associated with conventional fixed threshold systems of past missions, while significantly reducing weight and power. A brief description of the design as well as experimental results are presented.

A VLSI Image Processing Architecture Dedicated to Real-Time Quality Control Analysis in an Industrial Plant

In this paper, we present a VLSI architecture for real-time image processing in quality control industrial applications: automation of the visual inspection phase of mechanical parts treated by the Fluorescent Magnetic Particle Inspection method for structural-defect detection. The VLSI architecture implements a highly constrained neural network tailored for this specific application: the multi-layer perceptron with strictly local connections. The learning of the weights is performed off line by using the adaptive simulated-annealing algorithm. The neural network has been trained on real plant data: recognition results of the training and classification tasks compare favorably with those obtained by expert human operators.The VLSI architecture receives as input the image (taken on-line on the plant) of a mechanical part and it will find out if at least one structural surface defect is present. The VLSI architecture was optimized, through a set of transformations on the high-level VHDL specifications of the neural network algorithm, to reach real-time operating conditions. Following the proposed approach and the designed architecture, we designed and successfully tested a custom VLSI chip for the real-time implementation of the recognition task.

A 433-MHz 64-b quad-issue RISC microprocessor

A quad-issue custom VLSI microprocessor is described. This microprocessor implements the Alpha architecture and achieves an estimated performance of 13.3 SPECint9S and 18.4 SPECfp95 at 433 MHz. The 9.6 million transistor die measures 14.4 mm/spl times/14.5 mm, and is fabricated in a 0.35-/spl mu/m, four-metal layer CMOS process. This chip dissipates less than 25 W at 433 MHz using a 2.0 V internal power supply. The design was leveraged from a prior 300-MHz, 3.3-V, 0.50-/spl mu/m CMOS design. It includes several significant architectural enhancements and required circuit solutions for operation at 2.0 V. The chip will operate at nominal internal power supply voltages up to 2.5 V allowing improved performance at the cost of increased power consumption. At 2.5 V, the chip operates at 500 MHz and delivers 15.4 SPECint95 (est) and 21.1 SPECfp95 (est). This paper describes the chip implementation details and the strategy for efficiently migrating the existing design to the 0.35-/spl mu/m technology.