Custom IP Cores Research Articles

Cache timing attacks on NoC-based MPSoCs

Rising demands for increased performance, lower energy consumption, connectivity and programming flexibility are nowadays driving the platforms, so-called Multi-Processor Systems-on-Chips (MPSoCs). These platforms are composed of several processing elements, custom IP cores, and memories, all of which are in general interconnected by a Network-on-Chip (NoC). As attractive as these characteristics are, they introduce several security concerns, specially when applications with different trust and protection levels share resources. When a malicious software acquires access to an IP, it opens a door to external surveillance of the cache-memory, processing units and the NoC communication structure. The cache memory was already exploited by several authors in ASICs and Systems-on-Chips through Side-Channel Attacks (SCAs). In this work, we expand this concept, exploring the timing attacks on caches in the MPSoC scenario. We implement two well established attacks in the literature on a real hardware platform, the MPSoC Glass. Furthermore, we present the NoC as a novel vulnerability to increase attack efficiency, resulting in the Earthquake Attack. Results show that the attacks from literature can succeed inside the MPSoC, and obtain better results. Additionally, Earthquake improves the base attack by using the NoC timing attack, reducing the remaining attack complexity from 236.9 to 232 with 216.6 encryptions instead of 227.97.

The Design of IP Core for LCD Controller Based on SOPC

In this paper, it introduces the design and implementation of custom IP core for liquid crystal display (LCD) controller based on system on a programmable chip (SOPC) technology and Verilog hardware description language (HDL). The IP core can be put up as a general-purpose peripheral module to the Avalon Bus, communicating with the NIOS II through registers, and the underlying sequential logic for communicating with the external LCD liquid crystal module is automatically completed by the module. The driver does not need to care about the details of the underlying timing, it only needs to implement the read and write operations of the LCD data through register access, thus achieve the purpose of controlling the display content of the LCD. In addition to reducing the complexity of driver development, the design can also take full advantage of the parallel operation of hardware logic to improve the execution efficiency of the entire system and the throughput of processing tasks, especially in some occasions where high-speed image real-time processing is required. Simulations and experiments show that the IP core for LCD controller has good stability, versatility and compatibility.

FPGA-based wireless sensor nodes for vibration monitoring system and fault diagnosis

The use of wireless sensor networks (WSN) in different applications and domains is constantly growing. In the industrial applications, especially the monitoring of rotating machinery, WSN technology is mature enough to be considered as the most appropriate alternative to traditional wired systems due to a specific constraints related to the art itself. Given the importance of this area, the sensor nodes constituting industrial wireless sensor networks must meet some exigencies such as secure data transmission, high sampling rate and synchronous data acquisition, which require such minimum level of data processing capabilities. In the present work, we developed an FPGA-based wireless sensor node for a machine vibration monitoring system and fault diagnosis. The proposed wireless node is based on Xilinx Artix-7 XC7A35T FPGA circuit, connected via a Serial Peripheral Interface (SPI) to the RF transceiver nRF24L01+ as low-cost and low-power wireless radio module. An additional AES (Advanced Encryption Standard) block is implemented as custom IP core so that the transmitted data is highly secured. A solution is proposed in order to improve the synchronization using a sink node as master to trigger a simultaneous data acquisition in the network. To validate the node, experimental tests are performed on a rotating machine test bench with unbalance fault. The measurement results showed that the designed node met the requirements for synchronous data acquisition where a minimal error of 60 ns is reached.

Design of AD Controller Customized IP Core Based on FPGA

This design elaborates thedevelopment process of the custom IP core AD9280 controller based on FPGA. Thedesign uses FPGA as the core of the microcontroller, realizes the function ofAD controller by adopting the hardware description language,Verilog HDL and encapsulates it to the custom IP core in the SOPCBuilder. In the NIOS II, the application program interface (API) function ofthe AD controller software is used to access and control the hardware, thesoftware is written by using C language. The experimental results show thatthis custom IP core is feasible and flexible, fully reflects the advantages ofSOPC technology.

Embedded Linux platform for data acquisition systems

This scalable hardware–software system is designed and developed to explore the emerging open standards for data acquisition requirement of Tokamak experiments. To address the future need for a scalable data acquisition and control system for fusion experiments, we have explored the capability of software platform using Open Source Embedded Linux Operating System on a programmable hardware platform such as FPGA. The idea was to identify the platform which can be customizable, flexible and scalable to support the data acquisition system requirements. To do this, we have selected FPGA based reconfigurable and scalable hardware platform to design the system with Embedded Linux based operating system for flexibility in software development and Gigabit Ethernet interface for high speed data transactions. The proposed hardware–software platform using FPGA and Embedded Linux OS offers a single chip solution with processor, peripherals such ADC interface controller, Gigabit Ethernet controller, memory controller amongst other peripherals. The Embedded Linux platform for data acquisition is implemented and tested on a Virtex-5 FXT FPGA ML507 which has PowerPC 440 (PPC440) [2] hard block on FPGA. For this work, we have used the Linux Kernel version 2.6.34 with BSP support for the ML507 platform. It is downloaded from the Xilinx [1] GIT server. Cross-compiler tool chain is created using the Buildroot scripts. The Linux Kernel and Root File System are configured and compiled using the cross-tools to support the hardware platform. The Analog to Digital Converter (ADC) IO module is designed and interfaced with the ML507 through Xilinx Generic Interface (XGI) expansion headers. The Custom IP Core is designed and implemented in FPGA to interface the external ADC with DMA engine of the on-chip processor block. The data acquisition from ADC interface is successfully achieved and the captured data is sent to the host PC on mounted NFS share (Network File System) through LAN (Local Area Network). The detailed hardware and software design, development and testing results will be discussed in the paper.

Design of an FPGA-based embedded system for the ATLAS Tile Calorimeter front-end electronics test-bench

The portable test-bench for the certification of the ATLAS tile hadronic calorimeter front-end electronics has been redesigned for the present Long Shutdown (LS1) of LHC, improving its portability and expanding its functionalities. This paper presents a new test-bench based on a Xilinx Virtex-5 FPGA that implements an embedded system using a PowerPC 440 microprocessor hard core and custom IP cores. A light Linux version runs on the PowerPC microprocessor and handles the IP cores which implement the different functionalities needed to perform the desired tests such as TTCvi emulation, G-Link decoding, ADC control and data reception.

Design and Implementation Based the SOPC of the 2D-FFT Processor

This paper analyzed the principle of the two-dimensional FFT algorithm, and adopted the time domain extracted base 2D-FFT algorithm and CORDIC to achieve a one-dimensional FFT IP core in Quartus II platform, then used this IP core matrix transposition module to structure 2D-FFT core processing unit desired. In SOPC system, we adopted custom components and IP core packaging technology and adding the integration of the module. Completed the design of SOPC system, which was simulated and downloaded to the development board for verification and the test results were compared to the Matlab operation results. The simulation and test results showed that this design had a simple hardware structure, high throughput, high stability and a good prospect.