Custom Hardware Research Articles

Multiple Source Angle of Arrival Estimation Through Phase Interferometry

The evaluation of the Angle of Arrival (AoA) of a received signal is a basic tool for many RF location systems. This brief introduces a new technique for estimating the AoA via a phase interferometric approach when multiple sources are present. After briefly recalling some widespread algorithms and methods, the proposed technique is described from a mathematical point of view. This brief also reports the results of an experimental campaign, along with a comparison of the results with those obtained using the Estimation of Signal Parameters via Rotational Invariant Techniques (ESPRIT) and Root MUltiple SIgnal Classification (RMUSIC) algorithms. The experiments demonstrate that the proposed approach gives accurate results with low computational complexity, thus being eligible for direct implementation in digital custom hardware.

UAV-Aided Emergency Environmental Monitoring in Infrastructure-Less Areas: LoRa Mesh Networking Approach

Rapid acquisition of environmental parameters of emergency sites is crucial for emergency response. However, in areas where public ground networks do not provide sufficient coverage or are destroyed by disasters, the rapid backhaul of monitoring data from emergency sites is difficult. Due to the urgent demand for data collection in such areas, we propose an unmanned aerial vehicle (UAV)-aided emergency environmental monitoring system using a LoRa mesh networking approach, which can quickly build a large range of wireless communication networks suitable for small data transmission. First, we designed a LoRa-based mesh network protocol by using a custom slotted ALOHA medium access mechanism. Second, we designed and implemented a custom software and hardware platform of the monitoring system. The system adopts a communication mode, including multiple sensor nodes (SNs), multiple relay nodes (RNs), a gateway (GW), and a network server. Finally, we demonstrated the performance of the protocol and the system by in-lab and outdoor tests. The results show that when data rate is 0.293 kb/s, the line-of-sight 1-hop transmission distance is more than 10 km, and the 1-hop transmission delay is less than 6 s; the end-to-end delay has an upper bound, which can meet the real-time requirement of emergency response; the least upper bound of throughput per slot of our mesh protocol is much higher than that of LoRaWAN. Evaluation results also demonstrate the network robustness to environmental changes.

Design and Implementation of Synthetic Aperture Radar (SAR) Field-Programmable Gate Array (FPGA)-Based Processor

Synthetic aperture radar (SAR) is a unique imaging radar system that is capable of obtaining high-resolution images by using signal-processing techniques while operating in all weather and in the absence of a light source. The potential of SAR in a wide range of applications has led to new challenges in digital SAR processor design. On-board storage of SAR raw data is often not practical for real-time applications. The design of digital SAR processors is always restricted by the available space of the carrier system, data transfer rate, payload capacity and on-board power supplies. As reported in the literature, although customized hardware solutions could offer the desired performance, they are not feasible for low-volume production. This research aims to design and develop an efficient digital SAR processor by using field-programmable gate array (FPGA) with the consideration of hardware resources, processing speed and precision. In this paper, a hardware implementation of an FPGA-based SAR processor is presented. The implementation and architecture of the proposed SAR processor are highlighted in this paper. A MATLAB-based SAR processing range-Doppler algorithm (RDA) was developed as the benchmark for the development of an SAR processor. The target device, Altera Stratix IV GX FPGA EP4SGX230KF40C2, was selected for the design and implementation of an FPGA-based SAR processor. Comprehensive evaluations of the performance of the proposed SAR processor in terms of precision, timing performance and hardware resource utilizations are also presented. The proposed FPGA-based digital SAR processor achieves optimum performance in processing SAR signals for image formation. Evaluation shows that the designed SAR processor is capable of processing SAR images with ±1% difference error as compared to SAR images processed by MATLAB. The results also show a reduction in hardware usage via the implementation of an FPGA-based FFT/IFFT coprocessor. These promising results prove that the performance of the proposed processor is satisfactory and the achieved processing time, as well as the power consumption of the processor, outperformed existing implementations.

Fibular Strut Autograft as an Augmented Biological Plate: A New Modified Technique for Tibiocalcaneal Arthrodesis With Intramedullary Nail

Fibular Strut Autograft as an Augmented Biological Plate: A New Modified Technique for Tibiocalcaneal Arthrodesis With Intramedullary Nail

Cooperative distributed nonlinear model predictive control of a formation of differentially-driven mobile robots

Due to the increasing complexity of today’s tasks and the demand for higher performance and robustness, using a single robot is not always expedient in robotics applications. Therefore, having multiple autonomous robotic agents collaborate utilizing explicit communication is gaining more attention. The goal of this article is to develop a distributed algorithm that allows the formation control of multiple differentially-driven mobile robots. The formation control goal is formulated in a novel manner by leveraging results on the control of a single differentially-driven mobile robot, which is sophisticated due to the present non-holonomic constraint. This results in a nonlinear distributed control problem. The fundamental functionality of the developed algorithm is analyzed in simulation scenarios. The applicability to real-life scenarios is demonstrated through experiments with custom hardware. To the best of the authors’ knowledge, this is the first time that nonlinear distributed model predictive control is applied to a formation of differentially-driven mobile robots using a theoretically-founded cost function and, moreover, that the results are verified with hardware experiments.

Approximate Down-Sampling Strategy for Power-Constrained Intelligent Systems

In modern power constrained applications, as with most of those belonging to the Internet-of-Things world, custom hardware supports are ever more commonly adopted to deploy artificial intelligence algorithms. In these operating environments, limiting the power dissipation as much as possible is mandatory, even at the expense of reduced computational accuracy. In this paper we propose a novel prediction method to identify potential predominant features in convolutional layers followed by down-sampling layers, thus reducing the overall number of convolution calculations. This approximation down-sampling strategy has been exploited to design a custom hardware architecture for the inference of Convolutional Neural Network (CNN) models. The proposed approach has been applied to several benchmark CNN models and we achieved an overall energy saving of up to 70% with an accuracy loss lower than 3%, with respect to baseline designs. Performed experiments demonstrate that, when adopted to infer the Visual Geometry Group-16 (VGG16) network model, the proposed architecture implemented on a Xilinx Z-7045 chip and on the STM 28nm process technology dissipates only 680 and 21.9 mJ/frame, respectively. In both cases, the novel design overcomes several state-of-the-art competitors in terms of energy-accuracy drop product.

Flexible Memristive Devices Based on Graphene Quantum-Dot Nanocomposites

Artificial neural networks (ANNs) are attracting attention for their high performance in various fields, because increasing the network size improves its functioning. Since large-scale neural networks are difficult to implement on custom hardware, a two-dimensional (2D) structure is applied to an ANN in the form of a crossbar. We demonstrate a synapse crossbar device from recent research by applying a memristive system to neuromorphic chips. The system is designed using two-dimensional structures, graphene quantum dots (GQDs) and graphene oxide (GO). Raman spectrum analysis results indicate a D-band of 1421 cm−1 that occurs in the disorder; band is expressed as an atomic characteristic of carbon in the sp2 hybridized structure. There is also a G-band of 1518 cm−1 that corresponds to the graphite structure. The G bands measured for RGO-GQDs present significant GQD edge-dependent shifts with position. To avoid an abruptly-formed conduction path, effect of barrier layer on graphene/ITO interface was investigated. We confirmed the variation in the nanostructure in the RGO-GQD layers by analyzing them using HR-TEM. After applying a negative bias to the electrode, a crystalline RGO-GQD region formed, which a conductive path. Especially, a synaptic array for a neuromorphic chip with GQDs applied was demonstrated using a crossbar array.

Sine-Cosine Modulation for SSB Backscatter Radio Applications

The objective of this paper is to improve the efficiency and reliability of ambient backscatter. Specifically, this paper describes a novel tag-data modulation technique for backscattering 802.11-compliant interrogation signals. The technique is suitable for implementation in recently published Single Sideband (SSB) backscattering tag designs. The primary advantage is that the tag-data receiver need not be aware of the interrogating station’s data. This allows the tag to use any available 802.11 signal to backscatter its data. We also describe the demodulation algorithm necessary to extract tag-data at the receiver. A limitation is that commercial 802.11 receivers cannot directly demodulate tag data. At the same time, custom hardware will not be necessary, either. Simple modification to process the pre-detection data at standard 802.11 receivers will suffice. Although this paper describes the novel tag-data modulation specifically for incident 802.11 signals, the technique is suitable for other ambient signals as well.

FiCA: A Fixed-Point Custom Architecture FastICA for Real-Time and Latency-Sensitive Applications.

Independent Component Analysis (ICA) is a common method exploited in different biomedical signal processing applications, especially in noise removal of electroencephalography (EEG) signals. Among different existing ICA algorithms, FastICA is a popular method with less complexity, which makes it more suitable for practical implementation. However, and due to its inherent computationally intensive nature, development of a custom FastICA hardware is the best way to utilize it in high-performance real-time applications. On the other hand, development of a custom hardware in a fixed-point manner is also a complex and challenging task due to the algorithm's iterative nature. Moreover, the algorithm intrinsically suffers from some convergence problems which prevents to be practically exploited in latency-sensitive applications. In this paper, a fixed-point fully customized, scalable, and high-performance FastICA processor architecture has been presented. The proposed architecture is developed in an algorithm-aware manner to mitigate the inherent FastICA algorithmic failures. The synthesis results in a 90 nm technology show that the design proposes a computational time of 0.32 ms to perform an 8-channel ICA with a frequency of 555 MHz. The performance-related measurements prove that its normalized throughput is 10 times more, compared to the closest rival.

Custom Hardware Inference Accelerator for TensorFlow Lite for Microcontrollers

In recent years, the need for the efficient deployment of Neural Networks (NN) on edge devices has been steadily increasing. However, the high computational demand required for Machine Learning (ML) inference on tiny microcontroller-based IoT devices avoids a direct software deployment on such resource-constrained edge devices. Therefore, various custom and application-specific NN hardware accelerators have been proposed to enable real-time Machine Learning (ML) inference on low-power and resource-limited edge devices. Efficient mapping of the computational load onto hardware and software resources is a key challenge for performance improvement while keeping low power and a low area footprint. High performance and yet low power embedded processors may be attained via the usage of hardware acceleration. This paper presents an efficient hardware-software framework to accelerate machine learning inference on edge devices using a modified TensorFlow Lite for Microcontroller (TFLM) model running on a Microcontroller (MCU) and a dedicated Neural Processing Unit (NPU) custom hardware accelerator, referred to as MCU-NPU. The proposed framework supports weight compression of pruned quantized NN models and exploits the pruned model sparsity to reduce computational complexity further. The proposed methodology has been evaluated by employing the MCU-NPU acceleration for various TFLM-based NN architectures using the common MLPerf Tiny benchmark. Experimental results demonstrate a significant speedup of up to 724x compared to a pure software implementation. For example, the resulting runtime for the CIFAR-10 classification is reduced from about 20 sec to only 37 ms using the proposed hardware acceleration. Moreover, the proposed hardware accelerator outperforms all the reference models optimized for edge devices in terms of inference runtime.

IEEE Open Journal of the Solid-State Circuits Society Special Section on Custom Circuits and Architectures for Energy-Efficient Machine Learning

Machine learning (ML) and artificial intelligence (AI) have been successful in many practical applications, e.g., image/speech/video recognition, object detection/tracking, natural language processing, etc. To efficiently execute such AI/ML algorithms, there have been large advances in custom hardware accelerator designs, such as digital systolic arrays of processing engines (PEs), and analog or digital circuits for in-/near-memory computing for deep neural networks (DNNs) <xref ref-type="bibr" rid="ref1" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[1]</xref> , <xref ref-type="bibr" rid="ref2" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">[2]</xref> .

Implementation of a DPU-Based Intelligent Thermal Imaging Hardware Accelerator on FPGA

Thermal imaging has many applications that all leverage from the heat map that can be constructed using this type of imaging. It can be used in Internet of Things (IoT) applications to detect the features of surroundings. In such a case, Deep Neural Networks (DNNs) can be used to carry out many visual analysis tasks which can provide the system with the capacity to make decisions. However, due to their huge computational cost, such networks are recommended to exploit custom hardware platforms to accelerate their inference as well as reduce the overall energy consumption of the system. In this work, an energy adaptive system is proposed, which can intelligently configure itself based on the battery energy level. Besides achieving a maximum speed increase that equals 6.38×, the proposed system achieves significant energy that is reduced by 97.81% compared to a conventional general-purpose CPU.

Approaches for FPGA Design Assurance

Field-Programmable Gate Arrays (FPGAs) are widely used for custom hardware implementations, including in many security-sensitive industries, such as defense, communications, transportation, medical, and more. Compiling source hardware descriptions to FPGA bitstreams requires the use of complex computer-aided design (CAD) tools. These tools are typically proprietary and closed-source, and it is not possible to easily determine that the produced bitstream is equivalent to the source design. In this work, we present various FPGA design flows that leverage pre-synthesizing or pre-implementing parts of the design, combined with open-source synthesis tools, bitstream-to-netlist tools, and commercial equivalence-checking tools, to verify that a produced hardware design is equivalent to the designer’s source design. We evaluate these different design flows on several benchmark circuits and demonstrate that they are effective at detecting malicious modifications made to the design during compilation. We compare our proposed design flows with baseline commercial design flows and measure the overheads to area and runtime.

A remote laboratory course on experimental human physiology using wearable technology.

To help educators deliver their physiology laboratory courses remotely, we developed an inexpensive, customizable hardware kit along with freely available teaching resources. We based the course design on four principles that should allow students to conduct insightful experiments on different physiological systems. First, the experimental setup should not be constrained to laboratory environments. Second, students should be able to take this course without prior coding and electronics experience. Third, the hardware kit should be relatively inexpensive, and all other resources should be freely available. Fourth, all resources should be customizable for educators. The hardware kit consists of commercially available electronic components, with a microcontroller as its hub (Arduino friendly). All measurement systems can be assembled without soldering. The hardware kit is cost-effective (approximately the cost of a textbook) and can be customized depending upon instructional needs. All software is freely available, and we share all necessary codes in open-access online repositories for simple use and customizability. All lab manuals and additional video tutorials are also freely available online and customizable. In our particular course, we have weekly asynchronous physiology lectures and one synchronous laboratory session, where students can get help with their equipment. In this article, we only focus on the novel and open-source laboratory part of the course. The laboratory includes four units [data acquisition, ECG, electromyography (EMG), activity classification] and one final project. It is our intent that these resources will allow other educators to rapidly implement their own remote physiology laboratories or to extend our work into other pedagogical applications of wearable technology.

Hybrid Architectural Network Implementation to Realize a Fire Evacuation Path with 2.4 GHz Zigbee and LoRa

The Internet of Things (IoT) is playing a significant role in realizing real monitoring. In fire safety and evacuation, early fire event detection using IoT-enabled sensors may help to control and minimize further consequences of the fire accident. In this study, we propose a hybrid architecture based on 2.4 GHz Zigbee and long-range (LoRa) for real-time fire detection, monitoring, and assisting in the safe evacuation of the building. The architecture comprises five different components, namely: end device, evacuation path display controller, safety operation controller, vision node, and gateway. The end device and vision node provide real-time sensory data and visuals that provide details of fire occurrence. The evacuation path display controller and the safety operation controller based on the 2.4 GHz Zigbee receive data from the end device and make the decision accordingly. In addition, a Zigbee simulation is performed on the OPNET simulator to analyze the network parameters such as throughput, retransmission attempts, medium access (MAC) queue size and queue delay, and packet delivery ratio (PDR). The evaluation metrics of link budget and ToA of LoRa are also calculated by varying the code rate and spreading factor. To realize the proposed architecture, customization of hardware is carried out with the development of hardware prototypes. Dijkstra’s shortest path algorithm is implemented in the evacuation path display controller to provide the shortest evacuation path during a fire incident. The hardware of the system is implemented in real-time, and the system provides real-time sensor data along with the evacuation path.

Abstract 10086: Cardiac Intravital Microscopy Enables Quantitative Mapping of Capillary-Level Blood Flow in the Murine Heart

Introduction: Coronary microvascular disease (CMD) is increasingly appreciated as a contributor to adverse cardiovascular outcomes, but underlying mechanisms of CMD remain poorly understood. Investigation of CMD in animal models is limited by a lack of techniques to quantify flow in the heart. We assessed the hypothesis that intravital microscopy (IVM) can enable in vivo imaging of red blood cell (RBC) flow profiles in the coronary microcirculation at cellular resolution. Methods: C57BL/6 mice (n=20) were used to develop cardiac IVM protocols. Cardiomyocyte membrane staining was achieved using intravenous injection of a voltage dye (di-2-anepeq). RBC labeling was done by ex-vivo staining of cells with Ter119 followed by transfusion. IVM was performed through a thoracotomy with animals anesthetized and ventilated. Confocal and two-photon microscopy was done using a custom tissue stabilizer and an Olympus FV1000MPE microscope synchronized to physiologic signals using custom hardware and software and cardiac pacing protocols. Images were analyzed in MATLAB to extract myocyte contractile properties, capillary diameter, and capillary flow properties. Results: Using cardiac and respiratory gating, images with cellular resolution could be measured in the beating heart at all phases of the cardiac cycle. This enabled quantification of cardiomyocyte contractile function and capillary diameter and widefield imaging by stitching of several images (Fig. 1A). Tracking of RBCs over serial images allowed quantification of RBC velocity across multiple capillaries simultaneously (Fig. 1B). Conclusion: Cardiac IVM can provide quantification of cardiac function and blood flow at the single cell scale and will provide an exciting tool for investigating CMD in models of heart disease.

Correction of Traumatic Transverse Mandibular Widening With Interdental Wiring.

Mandibular symphysis fractures pose several technical challenges for the craniomaxillofacial surgeon. One classic challenge is restoration of the transverse dimension when the mandible is widened secondary to splaying of the lingual cortex. Failure to diagnose or correct this problem can result in widening of the lower facial third, inadequate fracture reduction, and/or a malocclusion. Surgeons have traditionally utilized techniques such as manual pressure to the rami or lingual splint application to address transverse defects intraoperatively. However, these methods may be inadequate in situations with significant widening, such as in the case of concomitant subcondylar fractures. More recently, virtual surgical planning and custom hardware have been utilized to address mandibular widening, though this method also has various shortcomings. In this technical note, the authors present a simple technique using interdental wiring to precisely control mandibular width intraoperatively. The technique is cost effective, does not require an assistant, and can be used in conjunction with any of the above methods. The authors also present a case of secondary reconstruction in which use of this technique was necessary given a large degree of mandibular widening not amenable to reduction and fixation with manual pressure alone.

Usability and performance validation of an ultra-lightweight and versatile untethered robotic ankle exoskeleton

BackgroundAnkle exoskeletons can improve walking mechanics and energetics, but few untethered devices have demonstrated improved performance and usability across a wide range of users and terrains. Our goal was to design and validate a lightweight untethered ankle exoskeleton that was effective across moderate-to-high intensity ambulation in children through adults with and without walking impairment.MethodsFollowing benchtop validation of custom hardware, we assessed the group-level improvements in walking economy while wearing the device in a diverse unimpaired cohort (n = 6, body mass = 42–92 kg). We also conducted a maximal exertion experiment on a stair stepping machine in a small cohort of individuals with cerebral palsy (CP, n = 5, age = 11–33 years, GMFCS I-III, body mass = 40–71 kg). Device usability metrics (device don and setup times and System Usability Score) were assessed in both cohorts.ResultsThere was a 9.9 ± 2.6% (p = 0.012, range = 0–18%) reduction in metabolic power during exoskeleton-assisted inclined walking compared to no device in the unimpaired cohort. The cohort with CP was able to ascend 38.4 ± 23.6% (p = 0.013, range = 3–132%) more floors compared to no device without increasing metabolic power (p = 0.49) or perceived exertion (p = 0.50). Users with CP had mean device don and setup times of 3.5 ± 0.7 min and 28 ± 6 s, respectively. Unimpaired users had a mean don time of 1.5 ± 0.2 min and setup time of 14 ± 1 s. The average exoskeleton score on the System Usability Scale was 81.8 ± 8.4 (“excellent”).ConclusionsOur battery-powered ankle exoskeleton was easy to use for our participants, with initial evidence supporting effectiveness across different terrains for unimpaired adults, and children and adults with CP.Trial registration Prospectively registered at ClinicalTrials.gov (NCT04119063) on October 8, 2019.

Sustaining accurate detection of phishing URLs using SDN and feature selection approaches

Phishing is an online fraud that deceives visitors by impersonating a legitimate website to steal their confidential or personal information. This is a well-known form of cybercrime. With the aim of detecting phishing sites, several phishing site detection techniques have recently been created. However, it fails to achieve the desired goal and has a large number of drawbacks, including low accuracy, long learning curve, and low-power embedded hardware. For covering such drawbacks, this work proposes an efficient URLs Phishing detection technique. Our technique depends on Software Defined Network (SDN) technology, clustering and feature method, and Conventional Neural Network (CNN) algorithm. Feature selection technique is based on Recursive Feature Elimination (RFE) with Support Vector Machine (SVM) algorithm. The SDN is used to transfer the URLs phishing detection process out of the user's hardware to the controller layer, continuously train on new data, and then send its outcomes to the SDN-Switches. RFE-SVM and CNN are used to increase accuracy of phishing detection. Therefore, the proposal model does not require retrieving the content of the target website or using any third-party services. It captures the information and sequential patterns of URL strings without requiring a prior knowledge about phishing, and then uses the sequential pattern features to quickly classify the actual URL. The experimental results showed that our proposal highlighted the robustness and accuracy in distinguishing between phishing and legitimate sites. Our suggestion achieves 99.5% phishing detection accuracy.

WPAN and IoT Enabled Automation to Authenticate Ignition of Vehicle in Perspective of Smart Cities.

Currently, two-wheelers are the most popular mode of transportation, driven by the majority the people. Research by the World Health Organization (WHO) identifies that most two-wheeler deaths are caused due to not wearing a helmet. However, the advancement in sensors and wireless communication technology empowers one to monitor physical things such as helmets through wireless technology. Motivated by these aspects, this article proposes a wireless personal network and an Internet of Things assisted system for automating the ignition of two-wheelers with authorization and authentication through the helmet. The authentication and authorization are realized with the assistance of a helmet node and a two-wheeler node based on 2.4 GHz RF communication. The helmet node is embedded with three flex sensors utilized to experiment with different age groups and under different temperature conditions. The statistical data collected during the experiment are utilized to identify the appropriate threshold value through a t-test hypothesis for igniting the two-wheelers. The threshold value obtained after the t-test is logged in the helmet node for initiating the communication with the two-wheeler node. The pairing of the helmet node along with the RFID key is achieved through 2.4 GHZ RF communication. During real-time implementation, the helmet node updates the status to the server and LABVIEW data logger, after wearing the helmet. Along with the customization of hardware, a LABVIEW data logger is designed to visualize the data on the server side.