Current-steering Digital-to-analog Converter Research Articles

Expanding the time-interleaving design capabilities: A 28 GS/s 4-bit time-interleaved current-steering DAC case study

In this work, a novel approach of designing high-speed time-interleaved Digital-to-Analog Converters (DACs), that exploits high-order time-interleaved factors, was proposed. The presented time-interleaving design approach is based on the current superposition principle, capable of expanding the time-interleaved factor of DACs without compromising the conversion linearity and accuracy. For the validation of the proposed design approach, a 28 GS/s 4-bit 4 × Time-Interleaved current-steering DAC was designed using a 22 nm Fully-Depleted Silicon-On-Insulator (FDSOI) CMOS process node. Post-layout simulations were carried out by developing a custom, hybrid RC/RLCk parasitic extraction methodology, capable of capturing all possible layout parasitic effects due to the high conversion speed of the designed DAC. Using the proposed approach, the designed time-interleaved DAC was capable of achieving ENOB>3.83 bits, SFDR>28.7 dBc for fin≤1.75 GHz, with no missing codes and a low power consumption of Pdiss=3.1 mW/core.

Modeling and Mitigating Output-Dependent Modulation in Current-Steering DAC Based on Differential-Quad Switching Scheme

This brief presents a comprehensive analysis of the output-dependent modulation (ODM) in a current-steering digital-to-analog converter (CS-DAC) based on the differential-quad switching (DQS) structure. A mathematical model is proposed to accurately describe ODM, which is categorized into two types: output transition errors and boundary effect errors. A novel approach of adding isolation devices is introduced and reinterpreted to mitigate the effect of ODM. The simulation results indicate that the inclusion of isolation devices efficiently suppresses the odd harmonics at mid-to-high frequency by a value that is 13 dB lower than before. Experimental validation is conducted on a 16-bit 250 MS/s CS-DAC fabricated in a 180 nm process.

A 12-Bit 1.2-GS/s Current-Steering DAC in 45-NM CMOS Technology

This research paper presents a 12-bit 8–4-segmented current-steering DAC (digital-to-analog converter) that offers notable advantages, particularly in terms of its reduced power consumption compared to other similar designs. The exceptional performance of our DAC can be attributed to two key factors: the use of a thermometer encoder and an efficient digital input bit segmentation. These features contribute to enhanced precision and reduced power requirements, setting our DAC apart from the existing solutions in the field. These enhancements significantly reduce glitches and improve the accuracy of the DAC’s output. DAC dissipates a total power of about 44.95[Formula: see text]mW when running at a sample rate of 1.2[Formula: see text]GHz with the CMOS technology of 45[Formula: see text]nm. While the supply input voltage is held constant at 1.2[Formula: see text]V, the DAC’s digital input is pulsating in nature in which the ON voltage is 1[Formula: see text]V and OFF voltage is 0[Formula: see text]V. Also, the DAC has a spurious-free dynamic range (SFDR) of 41.77[Formula: see text]dB.

Design and analysis of 4-bit low-power, high-performance current steering DAC implemented using CNT-GDI logic

This work proposes a 4-bit unary weighted current steering digital to analog converter (CS-DAC) with minimal integral nonlinearity (INL) error, less power consumption, and low glitch area. The input to the differential switch is through the thermometer decoder designed using GDI (Gate Input diffusion) logic, which lowers the power consumption and glitch area (also known as glitch energy) to 7.7nW and 0.0038 pVs respectively. Additionally, this unary decoder is used in the digital block of the proposed CS-DAC to lower the overall space and power consumption. The proposed circuitry employs 32 nm technology CNTFET technology. The comparative analysis of the CNTFET based proposed unary decoder design has shown a significant improvement of various performance measuring parameters. The power consumption, latency, and PDP has got substantially reduced by ∼94 %, ∼86 %, and ∼99 % in comparison to the conventional MOSFET based circuitry. In addition, it has been observed that in the proposed CNTFET GDI logic-based CS-DAC the INL, and differential non linearity (DNL) have got decreased by ∼89 % and ∼92 % respectively in comparison to the conventional MOS-based CS-DAC.Further, the dynamic performance measuring parameter like Spurious Free Dynamic Range (SFDR) has got increased by 41.7 % in comparison to the conventional CS-DAC. With a single 0.9 V supply voltage, the proposed DAC dissipates ∼100 % less power as compared to conventional CMOS-based CS-DAC.

A 10-bit CS-DAC using Fully Random Rotation based DEM and code independent output impedance compensation

This article presents a low power high dynamic performance 10-bit Current Steering Digital-to-Analog Converter (CS-DAC), which utilizes a novel Fully Random Rotation-based Dynamic Element Matching (FRR-DEM) technique and Code Independent Impedance Compensation (CIIC) method. The mismatch induced non-linearities are suppressed by proposed FRR-DEM , while at high frequency, the distortion due to code dependent load variation is compensated by CIIC technique to achieve the high Spurious Free Dynamic Range (SFDR). The FRR-DEM efficiently performs the rotation and binary to thermometer conversion of input Upper Least Significant Bits(ULSB) and Most Significant Bits (MSB) in a random fashion. In view of digital area complexity, this randomizer utilizes minimum number of transistors compared to the conventional state-of-the-art DEM DACs without compromising the dynamic performances and also it adds an additional level to averaging out the amplitude mismatch errors. The complete CS-DAC is designed using 180 nm CMOS process and the post-layout mismatch based simulation results are presented. This DAC achieves SFDR of more than 66 dB at 500 MS/s sampling frequency over entire Nyquist band with a 17 dB improvement from the conventional DAC. The proposed DAC acquires an active area of 0.31 mm2 and the post-layout simulated power consumption is 23 mW from a single 1.8 V supply.

A Model-Based Approach Digital Pre-Distortion Method for Current-Steering Digital-to-Analog Converters

This paper presents a novel static digital pre-distortion (DPD) method for a current-steering digital-to-analog converter (CS-DAC). The proposed method utilizes the knowledge of the current cell array architecture to calculate the static mismatch currents of the cells. The mismatch values are stored in memory and added to the original input code to generate the new pre-distorted input word. The converter corrects the static error with its own current cells without incorporating an additional calibration DAC (CALDAC) or programmable current sources. This results in a reduction in area, power and simulation run times because of the simpler circuit design. An Overflow-Cell-Selection (OCS) is introduced as a novel solution to further enhance the static linearity of the converter. It also can be implemented as a software solution for already existing DAC designs which do not have an integrated DPD and lab/measurement equipment (e.g., arbitrary wave generator (AWG)). This poses as a strong differentiation factor compared to other state-of-the-art static DPD methods. The evaluation of the proposed DPD is done via simulations in MATLAB and on- chip measurements with a 14-bit CS-DAC in 16 nm. Single tone measurements show a performance gain of the total harmonic distortion (THD) of 12 dB.

High SFDR Current-Steering DAC With Splitting-and-Binary Segmented Architecture and Dynamic-Element-Matching Technique

This brief presents a current-steering digital-to-analog converter (DAC) with “4-bit splitting +8-bit binary” segmented topology. The proposed splitting decoding method can optimize the differential nonlinearity and output glitches of the DAC with a more simplified circuit scale than unary decoding. With a data-transmission topology, the splitting decoder has a low latency and accommodates fast synchronization control of current source switches. Moreover, the dynamic element matching (DEM) technique is used to suppress the harmonic distortion caused by the splitting current source mismatch. The DAC is designed using 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS technology and occupies an area of 452.82 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times491.76\,\,\mu \text{m}$ </tex-math></inline-formula> . With a 1.8 V analog supply and a 1.2 V digital supply, the DAC dissipates 12.2 mW at 500 MS/s. The spurious-free dynamic range of the DAC improves from 63.18 dB to 73.30 dB using DEM technique for an output signal of 8.30 MHz and by 8-10 dB within the Nyquist bandwidth.

A 12-Bit Current-Steering DAC With Unary- Splitting -Binary Segmented Architecture and Improved Decoding Circuit Topology

This article presents a “three unary bits +five splitting bits + four binary bits” segmented 500-MS/s current-steering digital-to-analog converter (DAC). The proposed splitting decoding method is between the unary decoding and binary decoding, in terms of number of switched elements. It can optimize the differential nonlinearity and output glitches of DAC, with a more simplified circuit scale than unary decoding method. Due to the data-transmission topology, both the proposed thermometer and splitting decoders feature lower transistor count and occupy less area than other competitors. Their low latency accommodates to fast synchronization control of current source switches and its beneficial to the spurious-free dynamic range (SFDR) improvement of DAC. When implemented in a 0.18- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> CMOS process, the 12-bit DAC occupies an active area of 536 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,340\,\,\mu \text{m}$ </tex-math></inline-formula> , with the proposed decoders occupying only 28 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}\,\,\times \,\,75\,\,\mu \text{m}$ </tex-math></inline-formula> . The DAC dissipates 17.20 mW at 500 MS/s with a 1.8-V analog supply and a 1.2-V digital supply. The differential and integral nonlinearities are measured to be 0.28 and 1.16 LSB, respectively. The DAC also features SFDRs of 68.83 and 62.06 dB for input signals of 6.34 and 239.74 MHz, respectively.

A Pairwise Swap Enabled Randomized DEM Addressing Intersegment Mismatch for Current Steering Digital-to-Analog Converters

Mismatch-based nonlinear distortion greatly influences the accuracy and spurious-free dynamic range (SFDR) of current steering digital-to-analog converters (CS-DACs). Dynamic element matching (DEM) is an intelligent technique that reduces both amplitude and timing mismatch errors. In conventional DEM DACs, further enhancement of SFDR at higher frequencies is constrained due to the presence of intersegment mismatch errors in separate segmented structures. In this article, a pairwise swap enabled randomized DEM (PSER-DEM) technique is proposed to address the intersegment mismatch effect in segmented CS-DAC. This technique uses both randomization and swapping between row and column elements of current source cells for selecting the unit current source elements. A 6-bit CS-DAC with the PSER-DEM technique has been implemented with the UMC 180-nm 1.8-V CMOS process. The proposed DAC architectures with circuit description and measurement results are demonstrated briefly. A 48.15-dB SFDR with more than 6-dB enhancement is achieved from the measurement result. The proposed architecture for 10-bit CS-DAC is presented with vigorous mismatch-based Monte Carlo simulation results, which shows more than 70-dB SFDR for the entire Nyquist range frequency with more than 7-dB improvement from the conventional DEM DACs. Along with the PSER-DEM technique, a signal-dependent randomization concept is proposed to reduce the element transition rate and switching activity of current cells, which reduced the power consumption up to 4 mW for oversampling DACs. A comparative assessment is presented with state-of-the-art literature on DEM DAC structures. The proposed method has exhibited superior performance, which signifies the suitability for high-speed and high-resolution CS-DACs.

A 12‐bit SC3 partially segmented current steering DAC with improved SFDR and bandwidth

AbstractA 12‐bit self cascode capacitor compensated (SC3) partial segmented current steering digital to analog converter (DAC) is proposed and implemented in standard 180‐nm CMOS technology. The effect of the output capacitance at a higher frequency of operation is analyzed. Based on the analysis, a self cascode transistor is connected on the top of the differential switch with an “always‐on” biasing without compromising the voltage headroom. Besides, a compensation capacitor is also used at the output to improve spur free dynamic range (SFDR), which is obtained as 108 dB when sampled at 800 MS/s. The proposed architecture also offers high output impedance by more than 10 times compared with the cascode device. The proposed design also enhances the bandwidth of the circuit and is obtained to be 4 GHz with a power supply rejection ratio (PSRR) of 43 dB. It also has a total harmonic distortion (THD) of &lt;3% up to input power of −4 dB and is also insensitive to process variations with a sensitivity of &lt;0.5%.

A Digitally Controlled Multichannel Spectrally Efficient Low-Power Transceiver for Ultra-Wideband Cognitive Radio Applications

A multichannel transceiver design with low hardware complexity, flexibility and efficient spectrum use intended for Impulse Radio (IR) Ultra-Wideband (UWB) apertures, is proposed in this paper. The transceiver supports 14 channels and is implemented in TSMC CMOS process. The transmitter adopts a symmetrical triangular narrow pulse generator, a multiband LC-VCO, a mixer and a Variable-Gain Amplifier. A digital control of transmitter output power and carrier frequency is achieved by a current-steering Digital-to-Analog Converter (CS-DAC). The receiver follows the noncoherent Energy Detection (ED) scheme including Low-Noise Amplifier (LNA) which takes the benefits of the body biasing technique to further reduce power consumption, squarer and comparator. The LNA achieves high gain of up to 30[Formula: see text]dB allowing to enhance the receiver sensitivity which is [Formula: see text]83.7[Formula: see text]dBm at 25[Formula: see text]Mbps. The transmitter provides output pulses with a width of 3[Formula: see text]ns, a pulse repetition rate of 20[Formula: see text]ns and a maximum Power Spectral Density (PSD) of [Formula: see text]42[Formula: see text]dBm/MHz. The power consumptions of transmitter and receiver are 35.6[Formula: see text]pJ/bit and 0.207[Formula: see text]nJ/bit at 25[Formula: see text]Mbps, respectively. Maximizing utilization of the scarce wireless spectrum, enhancing spectral flexibility and efficiency and reducing power consumption are the main contributions brought by this work, enabling this transceiver to be able to deal with the current debate on producing single multifunctional Cognitive Radio (CR) UWB systems.

A survey of high-speed high-resolution current steering DACs

Digital to analog converters (DAC) play an important role as a bridge connecting the analog world and the digital world. With the rapid development of wireless communication, wideband digital radar, and other emerging technologies, better performing high-speed high-resolution DACs are required. In those applications, signal bandwidth and high-frequency linearity often limited by data converters are the bottleneck of the system. This article reviews the state-of-the-art technologies of high-speed and high-resolution DACs reported in recent years. Comparisons are made between different architectures, circuit implementations and calibration techniques along with the figure of merit (FoM) results.

Unified Analog PUF and TRNG Based on Current-Steering DAC and VCO

This work presents a unified weak physical unclonable function (PUF) and a true random number generator (TRNG) based on the current-steering digital-to-analog converter (DAC) and ring voltage-controlled oscillator (VCO). Entropy source for the weak PUF is the mismatch between NMOS and PMOS transistors in a cascode current DAC as well as the mismatch between VCO quantizers, while entropy source for the TRNG is thermal noise in the DAC and VCO and clock jitter. Instead of using spatial entropy sources for the PUF, i.e., multiple unit PUF elements, the proposed architecture utilizes temporal entropy source by capturing the output of unit PUF element over multiple cycles, which reduces area significantly. A unified PUF/TRNG prototype is fabricated in 65-nm CMOS and consumes 0.36 pJ/bit at a throughput of 100 Mb/s. The PUF has a measured intra-HD of 0.0906 and inter-HD of 0.4859, while the raw TRNG bitstream has an entropy of 0.9991 and passes all the NIST statistical randomness tests.

A 10‐bit 500‐MS/s Current Steering DAC with Improved Random Layout

According to the segmented current steering Digital-to-analog converter (DAC), the influence of current mismatch and output impedance of the current array on the linearity of DAC is discussed by theoretical analysis and derivation. An optimized layout plan for the current source array randomizes all these unit current sources corresponding to each thermometer code, which can significantly reduce the fist-order and second-order systematic mismatch errors in the current source array, and improve the linearity performance of DAC. With the segmented structure of 6 bit thermometer code and 4 bit binary code, a 10-bit DAC is realized in a 0.18mm CMOS by using the above layout plan. The active area of this DAC is 620μm × 340μm. Operated at 1V digital supply and 1.8V analog supply, with 500 MS/s sampling rate, the measured power consumption of this DAC is 14.3mW. The measurement results show that the Differential nonlinearity (DNL) and the Integral nonlinearity (INL) of the DAC with this random layout scheme are 0.71 LSB and 1.02 LSB. With 500 MS/s sampling rate and 1.465MHz input frequency, the Spurious free dynamic range (SFDR) and the Effective number of bits (ENOB) are 65.6dB and 9.2 bit, respectively.

Cryogenic Current Steering DAC With Mitigated Variability

This letter presents an 8-b differential current steering digital-to-analog converter (DAC) for the cryogenic front-end of future quantum computers. Recently published characterization of CMOS technology reveals the deterioration of transistor matching properties at cryogenic temperatures. The preliminary study of the current mismatch in the FDSOI technology at 4.2 K allows proper sizing of the 255 current-source unit cells to mitigate nonlinearities and optimize the static DAC performance. Based on this study, we minimize the power consumption while maintaining the targeted nonlinearity, i.e., 7.3 $\mu \text{W}$ for DNL = 0.64 LSB. With a 6.6-mV output range and 26- $\mu \text{V}$ voltage step, our DAC is compatible with the foreseen requirements for fine-grain biasing a Si-based qubit matrix at an expected 100-MS/s on-chip output drive.

Design and Analysis of a 12-b Current-Steering DAC in a 14-nm FinFET Technology for 2G/3G/4G Cellular Applications

A 14-nm FinFET CMOS 12-b current-steering digital-to-analog converter (DAC) for 2G/3G/4G cellular applications is presented herein. Bit segmentations of a 6-bit thermometer and 6-bit binary coding are adopted, utilizing switching-order shuffling in combination with dynamic element matching (DEM) to suppress the spurious tones owing to the current-source mismatch in three-dimensional FinFETs. In addition, output switches are designed to achieve make-before-break operation with the proposed low crossing point level shifter. Moreover, an output full-scale current trimming method is applied to maximize the power efficiency of the envelope-tracking (ET). The active area of a single DAC is 0.036 mm2, its power consumption is 6.1 mW, and its SFDR is 80 dBc.

An 8-Bit Ultra-Low-Power, Low-Voltage Current Steering DAC Utilizing a New Segmented Structure

In this paper, an 8-bit ultra-low-power, low-voltage current steering digital-to-analog converter (DAC) is presented. The proposed DAC employs a new segmented structure that results in low integral nonlinearity (INL) and high spurious-free dynamic range (SFDR). Moreover, this DAC utilizes a low-voltage current cell. The low-voltage characteristic of the current cell is achieved by connecting the body of MOSFET switches to their sources. Utilizing a low supply voltage along with a low bias current in the current cells results in about 623.81-[Formula: see text]W power consumption in 140-MS/s sample rate, which is very small compared to previous reports. The post-layout simulation results in 180-nm CMOS technology and [Formula: see text]-V supply voltage with the sample rate of 140[Formula: see text]MS/s show SFDR [Formula: see text] 64.37[Formula: see text]dB in the Nyquist range. The differential nonlinearity (DNL) and INL of the presented DAC are 0.1254 LSB and 0.1491 LSB, respectively.

A robust calibration method for R-2R ladder-based current-steering DAC

A foreground calibration technique for high-resolution, high-speed R-2R ladder-based current-steering digital-to-analog converter (DAC) is proposed. This kind of converter suffers from both current source mismatch and resistor mismatch. It is proved mathematically that the mismatch effect of the network resistors can be mapped to auxiliary current sources in parallel to the main current sources. Then this current sources can be calibrated in such a way that the output seems to be near ideal. A 125 MHz, 14-bit current-steering DAC is designed in 0.18 μm CMOS with the proposed calibration scheme. Assuming a variance of ±10 Ω for 1kΩ network resistors and ±2% mismatch among current sources, the INL and DNL are improved from 13b and 26b respectively to 0.5b and 0.8b utilizing the calibration. The spurious-free-dynamic-range (SFDR) raises from 63.7 dB to 93.1 dB while SNDR improves from 60.7 dB to 84.2 dB. This occurs for a small power penalty, and this process is resettable for PVT changes.

Demystifying and Mitigating Code-Dependent Switching Distortions in Current-Steering DACs

This paper analyzes the intermodulation between the element transition rate and the output-dependent unit switching distortion, i.e., the switching distortion of one switching unit, in current-steering digital-to-analog converters (DACs). The analysis and experimental results reveal how this intermodulation affects the DAC linearity. Based on this, we also propose a technique, termed random pairwise swapping (RPS) to improve the linearity of dynamic-element-matching-decoded DACs. Compared with existing techniques, RPS needs no half-cycle RZ operations and, thus, has no related vulnerabilities. In addition, the RPS could deal with the mismatch between different channels effectively. A 14-bit experimental DAC is fabricated in a 65-nm CMOS process. Measured results at 1.0-GS/s show above 72-dBc SFDR within 422-MHz bandwidth and 8–10-dB image tone suppression by the proposed RPS technique. At 3.0 GS/s, the SFDR is over 60 dBc within 600-MHz bandwidth.

A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme

This paper describes a calibration-free/dynamic-element-matching-free 8-bit 2.4-GS/s single-core current-steering digital-to-analog converter (CS-DAC) featuring an integral nonlinearity of ±0.097 LSB (equivalent to ~11-bit accuracy), a differential nonlinearity of 0.15/−0.05 LSB, a spurious-free dynamic range of >47.8 dB across the Nyquist bandwidth of 1.13 GHz, and a power dissipation of 26.4 mW from 1.2-/2-V supplies. These attributes are achieved by our proposed distributed biasing scheme, which largely decouples two critical tradeoffs in the CS-DAC—the tradeoff between the output impedance of the current sources and their current mismatches and that between the current mismatches and the timing errors. To simplify the CS-DAC measurements and hence reduced costs associated with testing during manufacturing, we propose a custom built-in $8\times 2.4$ -Gb/s digital pattern generator (DPG) featuring low I/O pin count, no high-speed data I/O circuits, and low hardware complexity/size. The proposed 8-bit 2.4-GS/s CS-DAC with the built-in DPG is realized using a commercial 65-nm low-power CMOS process.