Current-steering Digital-to-analog Converter Research Articles

A 4-Bit 5 GS/s Current Steering DAC Integrated Circuit

In order to satisfy the higher and higher transmission rate and broadband requirement of modern communication, a 4-bit 5 GS/s digital-to-analog converter (DAC) integrated circuit is presented. The DAC circuit is based on current steering architecture and segmented with a 4 bit unary. The circuit is designed and analyzed in TSMC 0.18 μm CMOS technology. The chip size is 0.675 mm 0.525 mm. Simulation results show that the maximum integral nonlinearity (INL) is 0.15 LSB. The DAC can achieve a spurious-free dynamic range (SFDR) of 22.76 dB under a clock frequency of 5 GHz with an input signal frequency of 250 MHz, while the power consumption is 11.6 mW.

InP HBT/Si CMOS-Based 13-b 1.33-Gsps Digital-to-Analog Converter With > 70-dB SFDR

A prototype 13-b 1.33-Gsps digital-to-analog converter (DAC) implemented in a unique heterogeneous integration process (combining 0.45-μm InP HBT with 0.18-μm CMOS) is presented. Measured performance of greater than 70 dB SFDR is achieved across a 500-MHz bandwidth centered at 1 GHz (second Nyquist band). Heterogeneous integration enables each circuit element to be implemented in the transistor technology best suited to the circuit function. Low dc power is achieved by implementing the digital front-end in a standard silicon CMOS technology, while InP HBT technology is used to implement the high-speed/high-precision current-steering DAC core. The core DAC employs a segmented architecture with three unary most significant bits and an R-2R ladder for the ten least significant bits. No calibration circuitry is required to achieve better than 11 b of dc linearity. Dynamic performance is enhanced by employing an ultra-high-linearity return-to-zero (RZ) analog output deglitcher switch. Measured performance data for three different circuit design variations of the output switch (incorporating a varying mix of CMOS and InP HBT devices) is presented.

A 14-bit 250-MS/s current-steering CMOS digital-to-analog converter

A 14-bit 250-MS/s current-steering digital-to-analog converter (DAC) was fabricated in a 0.13 μm CMOS process. In conventional high-speed current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions in the code-dependent switching glitches. In this paper, the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero (TRI-DRRZ). Under 250-MS/s sampling rate, the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz. The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.

A 375 mW Multimode DAC-Based Transmitter With 2.2 GHz Signal Bandwidth and In-Band IM3<formula formulatype="inline"> <tex Notation="TeX">$ {<} {-}$</tex></formula>58 dBc in 40 nm CMOS

A 40 nm CMOS digital-to-analog converter (DAC) based multimode transmitter (MMTX) is presented. The transmitter can be operated in either narrow- or wideband applications. It has a maximum 2.2 GHz signal bandwidth and exhibits an in-band IM3 of less than - 58 dBc. The MMTX consists of a current-steering DAC with digital sinc equalization and rolloff compensation. By implementing high-speed, feed-forward pipelined digital logic and a distributed decoder, the DAC sampling rate extends to 5 GHz. A distributed regulator approach ensures preservation of the achieved wideband linearity in noisy embedded SoC environments. The MMTX can deliver up to +11 dBm of output power and exhibits 20 dB of analog power backoff with 1 dB steps and a precision better than ±0.1 dB. The MMTX consumes only 375 mW and occupies 1.65 mm2.

An INL Yield Model of the Digital-to-Analog Converter

The integral nonlinearity (INL) yield of any arbitrarily segmented digital-to-analog converter (DAC) has not been accurately modeled and requires long simulation time. This paper proposes an intuitive formulation of the INL yield that leads to a simple and accurate relation between the variation of the unit source element and the DAC yield with only a few fitting parameters. These parameters can be determined for varying number of bits and varying DAC segmentation. A table of parameters is provided that can be directly applied to determine the yield without additional simulation. The validity of the model and parameters is demonstrated for measured current distributions from a current-steering DAC fabricated in a 90-nm CMOS technology.

A 12-bit, low-voltage, nanoampere-based, ultralow-power, ultralow-glitch current-steering DAC for HDTV

In this paper, a novel 12-bit current-steering binary-weighted digital-to-analog converter (DAC) based on nanoampere bits is designed and modified for high-definition television (HDTV) applications. As a part of a widely used consumer appliance, it is aimed to be such designed to consume power as low as possible. Hence, as a distinguished idea, prime concentration is focused on the reduction of the currents providing the bits of the proposed DAC. To do this, current mirrors operating in the weak inversion region are arranged to establish the least significant bit (LSB) current as low as 10 nA while the power supply is also reduced to 1 V, resulting to an ultralow power of 52.9 μW. Many other powerful ideas are then deliberately combined to maintain both high speed and very low glitches required for HDTV application despite those ultralow currents and power. The result is a speed of 100 MS/s, an ultralow glitch of ≃10.91 fAs, |INL| ≤ 0.988 LSB, |DNL| ≤ 0.99 LSB, and a spurious-free dynamic range of ≃73 dB. These results caused the proposed DAC to execute a distinguished overall performance (defined as figure of merit) greatly better than some other advanced ones by outstanding ratios of 77 to 277,185. Hspice simulations with the SMIC 0.18-μm complementary metal-oxide semiconductor technology have been used to validate the proposed circuit. Performance evaluation of the proposed DAC versus Monte Carlo simulations and also a wide range of temperature variations proved both its well mismatch insensitivity and thermal stability.

A 6-bit Current-Steering DAC With Compound Current Cells for Both Communication and Rail-to-Rail Voltage-Source Applications

A compound current cell, with n-type, p-type, and bipolar properties, is proposed in this brief and utilized in a current-steering digital-to-analog converter (DAC) to satisfy the application of rail-to-rail voltage sources. In addition, the DAC with cells also has a high-speed fashion. Therefore, this brief presents a 6-bit CMOS current-steering DAC with cells for both communication and rail-to-rail voltage-source applications. Moreover, the effective output voltage step size is improved by appropriately switching these cells and connecting one of the gain control resisters, resulting in an about 6.4-mV step size in a 1.2-V supply. Furthermore, this DAC was implemented in a standard low-power 90-nm 1P9M CMOS technology with the active area of 0.045 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured spurious-free dynamic range is more than 36 dB over the Nyquist frequency at 3 GS/s and the DAC consumes 8.32 mW with a near-Nyquist sinusoidal output at the sampling rate of 3 GS/s.

A current-steering self-calibration 14-bit 100-MSPs DAC

This paper presents the design and implementation of a 14-bit, 100 MS/s CMOS digital-to-analog converter (DAC). Analog background self-calibration based on the concept of analog current trimming is introduced. A constant clock load switch driver, a calibration period randomization circuit and a return-to-zero output stage have been adopted to improve the dynamic performance. The chip has been manufactured in a SMIC 0.13-μm process and occupies 1.33 × 0.97 mm2 of the core area. The current consumption is 50 mA under 1.2/3.3 V dual power supplies for digital and analog, respectively. The measured differential and integral nonlinearity is 3.1 LSB and 4.3 LSB, respectively. The SFDR is 72.8 dB at a 1 MHz signal and a 100 MHz sampling frequency.

A Design of Linearity Built-in Self-Test for Current-Steering DAC

In this paper, a current-mode Built-In Self-Test (BIST) scheme is proposed for on-chip estimating static non-linearity errors in current-steering digital-to-analog converters (DACs). The proposed DAC BIST scheme is designed to verify a 10-bit segmented current-steering DAC, consist of a 5-bit coarse DAC and a 5-bit fine one. This proposed BIST scheme includes a current-mode sample-and-difference circuit to increase the sampling current accuracy and control a current-controlled oscillator (ICO). In addition, only 36 measurements are required by using the selected-code method rather than 1024 measurements for the conventionally-utilized all-code method. Compared to the conventionally-utilized all-code method, about 85-% reduction of test time can be achieved.

Current-Steering Digital-to-Analog Converters: Functional Specifications, Design Basics, and Behavioral Modeling

Functional specifications and design basics for current-steering digital-to-analog converters (DACs) are covered. An outline of digital-to-analog conversion principles, together with fundamental current-steering DAC architectures, are briefly explained. A generalized design flow for DACs and design basics for current-steering architectures, together with a universal SIMULINK®-based behavioral model useful for the block-level simulation of a current-steering DAC, are described.

Low-Cost 14-Bit Current-Steering DAC With a Randomized Thermometer-Coding Method

A dynamic element-matching (DEM) method, i.e., randomized thermometer coding (RTC), for low-cost current-steering digital-to-analog converter (DAC) design is proposed. The proposed RTC method exhibits randomized starting-element selection, consecutive-element selection, and low-element switching activity. It can be used to significantly suppress the harmonic distortion caused by a large mismatch of small-area transistors, and, thus, very low cost DACs can be realized. With the proposed RTC, a 14-bit current-steering DAC is implemented in a 1P6M 0.18- mum 1.8-V CMOS process. The measured spurious-free dynamic range (SFDR) exceeds 80 dB. The measurement results showed that RTC improves the SFDR by more than 16 dB. The DAC has an active area of less than 0.28 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The proposed DAC achieves a smaller active area than state-of-the-art 12- to 14-bit DACs.

A small area 8 bits 50 MHz CMOS DAC for Bluetooth transmitter

This paper presents a small-area CMOS current-steering segmented digital-to-analog converter (DAC) design intended for RF transmitters in 2.45 GHz Bluetooth applications. The current-source design strategy is based on an iterative scheme whose variables are adjusted in a simple way, minimizing the area and the power consumption, and meeting the design specifications. A theoretical analysis of static-dynamic requirements and a new layout strategy to attain a small-area current-steering DAC are included. The DAC was designed and implemented in 0.35 μm CMOS technology, requiring an active area of just 200 μm × 200 μm. Experimental results, with a full-scale output current of 700 μA and a 3.3 V power supply, showed a spurious-free dynamic range of 58 dB for a 1 MHz output sine wave and sampling frequency of 50 MHz, with differential and integral nonlinearity of 0.3 and 0.37 LSB, respectively.

A 12-Bit Cryogenic and Radiation-Tolerant Digital-to-Analog Converter for Aerospace Extreme Environment Applications

This paper presents an 80-MHz 12-bit cryogenic low-power digital-to-analog converter (DAC) implemented in a 0.5-mum SiGe BiCMOS technology. The cryogenic DAC is capable of operating over an ultrawide temperature (UWT) ranging from -180degC to +120degC and under the high-energy particle radiation environment on the lunar surface. A bandgap voltage reference for the UWT applications is designed using SiGe heterojunction bipolar transistors, and the current-steering DAC is implemented using a segmented current source array. The design considerations for both extreme temperature and radiation environments are discussed. The cryogenic and radiation-tolerant DAC chip occupies a die area of 3.5 times 1.8 mm2 and consumes only 39.6 mW from a 3.3-V supply voltage. The maximum DAC sampling rate was measured at 80 MS/s at -180degC using a 40-pin dual in-line package.

A 10-bit 250-MS/s Binary-Weighted Current-Steering DAC

This paper studies the impact of segmentation on current-steering digital-to-analog converters (DACs). Segmentation may be used to improve the dynamic behavior of the converter but comes at a cost. A method for reducing the segmentation degree is given. The presented chip, a 10-bit binary-weighted current-steering DAC, has >60 dB SFDR at 250 MS/s from DC to Nyquist. At 62.5 MHz signal frequency and 250 MS/s, we operated the device in 9-bit unary, 1-bit binary-weighted mode. The obtained 60 dB SFDR in this measurement demonstrates that the binary nature of the converter did not limit the SFDR. The chip draws 4 mW from a dual 1.5 V/1.8 V supply plus load currents. The active area is less than 0.35 mm/sup 2/ in a standard 1P-5M 0.18-/spl mu/m 1.8-V CMOS process. Both INL and DNL are below 0.1 LSB.

The analysis and improvement of a current-steering DACs dynamic SFDR-I: the cell-dependent delay differences

For a high-accuracy current-steering digital-to-analog converters (DACs), the delay differences between the current sources is one of the major reasons that cause bad dynamic performance. In this paper, a mathematical model describing the impact of the delay differences on the DACs SFDR property is presented. The results are verified by comparison to behavioral-level simulations and to actual measurement data from published papers. Based on this analysis, the delay differences cancellation (DDC) technique to reduce the impact of the delay differences on the SFDR property is proposed and verified by simulation results.

Parallel-path digital-to-analog converters for Nyquist signal generation

Nyquist-rate digital-to-analog converters (DACs) can generate frequencies up to half the sampling frequency. It is, however, impractical to generate such high frequencies. Due to its nature, the converter will not only generate the desired signal itself but also, often undesired, image frequencies. For frequencies near the Nyquist frequency, an image with almost exactly the same amplitude appears very close to the signal. An extremely steep filter is required. Therefore, real-life systems do provide oversampling to locate the Nyquist image further away from the wanted signal. In practice, the signal frequency has to be reduced if the maximum sampling rate is reached. We propose a technique that conversely removes this Nyquist image so that only further away Nyquist images with lower amplitudes have to be filtered off. The proposed technique is applied to the design of a dual 6-bit binary current-steering DAC running at 250 MS/s.

A statistical methodology for the design of high-performance CMOS current-steering digital-to-analog converters

With the shrinking of device sizes, random device variations become a key factor limiting the performances of high-resolution complementary metal-oxide-semiconductor (CMOS) current-steering digital-to-analog converters (DACs). In this paper, we present a novel design methodology based on statistical modeling of MOS transistor drain current that allows designers to explore different DAC architectures and to study the effects of technological variations on system performance without using time-consuming Monte Carlo simulations. This technique requires as a first step the estimation of the mean value and the autocorrelation function of a single stochastic process. This stochastic process models the device drain current and summarizes all the random sources associated with the process/device variations since the current represents the effect of all of them. Subsequently, on the basis of such an approach, a behavioral model of current-steering DACs has been developed. Finally, the statistical simulation of static performances such as differential nonlinearity and integral nonlinearity has been carried out for different DAC architectures based on the behavioral model previously derived.

Modeling of CMOS digital-to-analog converters for telecommunication

This paper gives an overview of some of the effects caused by circuit mismatch and parasitics in binary weighted digital-to-analog converters (DACs), and, as a special case, a current-steering CMOS converter. Matlab is used as a behavior-level simulator. In telecommunications applications, the frequency-domain parameters are of the greatest importance. Therefore, the characterization of the device and its performance is determined by frequency parameters such as the signal-to-noise ratio, spurious-free dynamic range, multitone power ratio, etc. In this paper, we show how these frequency-domain parameters are affected when mismatch errors and finite output impedance are applied to a current-steering CMOS DAC. We discuss how static performance is affected when changing the size of the errors and fundamental circuit parameters. The impact of dynamic errors such as glitches, slewing, and bit skew is discussed. Measurement results from 14-bit DACs are also shown to illustrate the correlation with the modeling.