Abstract
In this paper, a novel 12-bit current-steering binary-weighted digital-to-analog converter (DAC) based on nanoampere bits is designed and modified for high-definition television (HDTV) applications. As a part of a widely used consumer appliance, it is aimed to be such designed to consume power as low as possible. Hence, as a distinguished idea, prime concentration is focused on the reduction of the currents providing the bits of the proposed DAC. To do this, current mirrors operating in the weak inversion region are arranged to establish the least significant bit (LSB) current as low as 10 nA while the power supply is also reduced to 1 V, resulting to an ultralow power of 52.9 μW. Many other powerful ideas are then deliberately combined to maintain both high speed and very low glitches required for HDTV application despite those ultralow currents and power. The result is a speed of 100 MS/s, an ultralow glitch of ≃10.91 fAs, |INL| ≤ 0.988 LSB, |DNL| ≤ 0.99 LSB, and a spurious-free dynamic range of ≃73 dB. These results caused the proposed DAC to execute a distinguished overall performance (defined as figure of merit) greatly better than some other advanced ones by outstanding ratios of 77 to 277,185. Hspice simulations with the SMIC 0.18-μm complementary metal-oxide semiconductor technology have been used to validate the proposed circuit. Performance evaluation of the proposed DAC versus Monte Carlo simulations and also a wide range of temperature variations proved both its well mismatch insensitivity and thermal stability.
Highlights
The digital-to-analog converter (DAC), and its different sub-blocks, is one of the most essential mixed-mode electronic building blocks which have been increasingly investigated during the last decades [1,2]
Hspice simulations with the SMIC 0.18-μm Complementary metal-oxide semiconductor (CMOS) technology have been used which validate the high performance of the proposed circuit with outstanding specifications: ultralow power ≃ 52.94 μW and ultralow glitch energy ≃ 10.914 fAs
The achieved differential nonlinearity (DNL), INL, and spurious-free dynamic range (SFDR) of the proposed DAC are shown in Figure 4a,b,c, respectively
Summary
The digital-to-analog converter (DAC), and its different sub-blocks, is one of the most essential mixed-mode electronic building blocks which have been increasingly investigated during the last decades [1,2]. Complementary metal-oxide semiconductor (CMOS) video DACs with low voltage, high speed, and high resolution are required to enhance video quality and to ensure feasibility of various video effects. This requires more complicated video systems which must incorporate high-speed signal processors. In high-definition television (HDTV) applications, DACs of more than 10 bits in resolution and faster than 80 MHz in speed are needed [1]. A current-steering structure is usually preferred for HDTV applications. This is mainly because the currentsteering structure has favorable speed, resolution, and power consumption specifications in comparison to other structures
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