Abstract
This letter presents an 8-b differential current steering digital-to-analog converter (DAC) for the cryogenic front-end of future quantum computers. Recently published characterization of CMOS technology reveals the deterioration of transistor matching properties at cryogenic temperatures. The preliminary study of the current mismatch in the FDSOI technology at 4.2 K allows proper sizing of the 255 current-source unit cells to mitigate nonlinearities and optimize the static DAC performance. Based on this study, we minimize the power consumption while maintaining the targeted nonlinearity, i.e., 7.3 $\mu \text{W}$ for DNL = 0.64 LSB. With a 6.6-mV output range and 26- $\mu \text{V}$ voltage step, our DAC is compatible with the foreseen requirements for fine-grain biasing a Si-based qubit matrix at an expected 100-MS/s on-chip output drive.
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