Current-reuse Technique Research Articles

Low-power ultra-wideband LNA employing CS–CD current-reuse and gain-controller resistor technique in 0.180-μm CMOS technology

In this paper, a low-power ultra-wideband low noise amplifier (LNA) is presented. The combination of dual resonance network and current-bleeding technique offers high and flat voltage gain and low noise figure (NF), and also, the gain-controller resistor technique causes better control of voltage gain to achieve flatter gain. Furthermore, the CS–CD (Common-Source Common-Drain) current-reuse technique provides output return loss reduction and eliminates buffer stage in LNA design. It has been shown that using this scheme, noticeable improvement has been obtained in the frequency range of 2–11 GHz. This improvement consists of minimum noise figure value as 2.5 dB, the maximum value of 4.2 dB and average noise figure lower than 3 dB in a wide frequency range, from 4 to 10 GHz. The proposed LNA achieves the average voltage gain of 12.35 dB with a variation of 0.85 dB in the frequency range of 2–11 GHz. Input and output return losses are below − 10 dB and IIP3 of the proposed structure is − 3 dBm. The proposed LNA consumes 9.52 mW in 1-V supply voltage. Moreover, the size of the structure is 0.54 mm2 in TSMC 180-nm technology.

Design Methodology of Ultra-Low-Power LC-VCOs for IoT Applications

A design methodology of CMOS LC voltage-controlled oscillator (VCO) is proposed in this paper. The relation between components and specifications of the LC-VCO is studied to easily identify its design trade-offs. This methodology has been applied to design ultra-low-power LC-VCOs for different frequency bands. An LC-VCO based on the current reuse technique has been realized with the proposed methodology in 0.13[Formula: see text][Formula: see text]m CMOS process. Measurements present an ultra-low power consumption of only 262[Formula: see text][Formula: see text]W drawn from 1[Formula: see text]V supply voltage. The measured frequency tuning range is about 10% between 2.179[Formula: see text]GHz and 2.409[Formula: see text]GHz. The post-layout simulation presents a phase noise (PN) of [Formula: see text][Formula: see text]dBc/Hz, while the measured PN is [Formula: see text][Formula: see text]dBc/Hz.

A CMOS low-noise active mixer with enhanced linearity and isolation by exploiting capacitive neutralization technique

In this paper, a broadband complementary metal–oxide–semiconductor (CMOS) active down-conversion mixer is presented. Specifically, a capacitor cross-coupled (CCC) transconductor serves as the input stage to reduce noise figure of the mixer while providing wideband input matching. Moreover, a capacitive neutralization technique is used to compensate the source-drain parasitic of input stage and boost loop gain of the transconductor, resulting in improved isolation and linearity. The current-reuse technique applied to the developed transconductor by stacked nMOS/pMOS architecture efficiently saves power consumption of the circuit. Implemented in the TSMC 28-nm CMOS process, post-simulations show that the proposed mixer provides a maximal conversion gain of 11.4 dB and an NF of 3.9–4.7 dB across RF input frequency range of 2–9.6 GHz. The average IIP3 of 5 dBm are obtained while the mixer core consumes 6.2 mW from a 1 V supply.

Fine-Grained Power Gating Using an MRAM-CMOS Non-Volatile Flip-Flop.

An area-efficient non-volatile flip flop (NVFF) is proposed. Two minimum-sized Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) and two magnetic tunnel junction (MTJ) devices are added on top of a conventional D flip-flop for temporary storage during the power-down. An area overhead of the temporary storage is minimized by reusing a part of the D flip-flop and an energy overhead is reduced by a current-reuse technique. In addition, two optimization strategies of the use of the proposed NVFF are proposed: (1) A module-based placement in a design phase for minimizing the area overhead; and (2) a dynamic write pulse modulation at runtime for reducing the energy overhead. We evaluated the proposed NVFF circuit using a compact MTJ model targeting an implementation in a 10 nm technology node. Results indicate that area overhead is normalized to the conventional flip flop. Compared to the best previously known NVFFs, the proposed circuit succeeded in reducing the area by and the energy by . The proposed placement strategy of the NVFF shows an improvement of nearly a factor of 2–18 in terms of area and energy, and the pulse duration modulation provides a further energy reduction depending on fault tolerance of programs.

A Wideband Flat Gain Low Noise Amplifier Using Active Inductor for Input Matching

This brief presents a wideband flat gain low noise amplifier using active inductor for input matching. The current reuse technique is adopted for the active inductor to reduce power consumption. The noise contribution of the active inductor is optimized by noise cancelling technique. The design is demonstrated in a standard 0.13- ${\mu }\text{m}$ CMOS process. The input return loss is better than 10 dB across the bandwidth of 0.7–4.6 GHz. The nominal gain is 10.1 dB with 1.3 dB gain variation in the passband. The measured noise figure is below 4.5 dB and the input referred third order intercept point is better than −1.6 dBm. The amplifier consumes 4.4 mA from a 1.4 V supply.

Low-Power and Low-Phase-Noise $G_{m}$ -Enhanced Current-Reuse Differential Colpitts VCO

A Colpitts voltage-controlled oscillator (VCO) is presented for low-power and low-phase-noise applications. The current efficiency of the proposed VCO is improved through ${g} _{{m}}$ -enhanced and current-reuse techniques. In addition, a clover-shaped inductor is employed to mitigate electromagnetic interference (EMI) effects. The VCO is implemented in a 0.18- ${ \mu }\text{m}$ CMOS process and is shown to operate at frequencies of 2.34 to 2.55 GHz with a tuning range of 8.6%. The prototype has a power dissipation of 1.4 mW and achieves a phase noise of −122.85 dBc/Hz at a 1 MHz frequency offset.

A Sub-1-V, 350-$\mu$ W, 6.5-dB Integrated NF Low-IF Receiver Front-End for IoT in 28-nm CMOS

This letter presents a highly efficient low-intermediate frequency receiver front-end for Internet-of-Things applications. The low-noise trans-impedance amplifier (LNTA) combines a transformer-based network for scaling up the source impedance together with passive gm -boosting and current-reuse techniques to achieve better noise and $12\times $ current saving compared with a common-gate (CG) stage. A complex channel-selection filter with center frequency and passband of 2 and 1.4 MHz, respectively, is implemented after the passive mixer with a gm -boosted CG stage. Built in 28-nm CMOS, the proposed receiver occupies an active area of 0.1 mm2, it is supplied with 0.9 V and consumes only 350 $\mu \text{W}$ , while showing a minimum NF of 6.2 dB at the channel of interest. The RF performance of the proposed receiver is very competitive with the state-of-the-art ultralow-power receivers, while it consumes the lowest power.

A 1-V 4.6-μW/channel Fully Differential Neural Recording Front-end IC with Current-controlled Pseudoresistor in 0.18-μm CMOS

This paper presents a fully differential implantable neural recording front-end IC for monitoring neural activities. Each analog front-end (AFE) consists of a low-noise amplifier (LNA), a variable gain amplifier (VGA), and a buffer. The output signal of the AFE is digitized through a successive approximation register analog-to-digital converter (SAR ADC). The LNA adopts the currentreuse technique to improve the current efficiency, achieving the power consumption as low as 0.95 μW. The implemented LNA has the gain of 40 dB, the lowpass cutoff frequency of 10 kHz, and the high-pass cutoff frequency of sub-1 Hz which is realized using the current-controlled pseudoresistor. The VGA controls the gain from 21.9 dB to 33.9 dB for efficient digitization while consuming the power of 0.35 μW. The buffer drives the capacitive DAC of the ADC and consumes the power of 3.28 μW. The fabricated AFE occupies the area of 0.11 ㎟/Channel and consumes 4.6 μW/Channel under 1-V supply voltage. Each channel achieves the input-referred noise of 2.88 μVSUBrms/SUB, the NEF of 2.38, and the NEF²VSUBDD/SUB of 5.67. The front-end IC is implemented in a standard 1P6M 0.18-mm CMOS process.

A Low-Power 0.6-V Quadrature VCO With a Coupling Current Reuse Technique

A novel quadrature voltage-controlled oscillator (QVCO) featuring low power consumption is proposed in this brief. By utilizing the coupling current reuse technique, the coupling current of one core is shared as a source to bias the quadrature coupling device in the other core. Thus, the coupling current consumption is eliminated. Moreover, the injected tank current is reshaped to reduce noise injection and increase efficiency. The coupling current reuse technique allows the proposed QVCO to achieve at least 50% power consumption decreasing compared to previous LC-QVCOs without sacrifices of phase noise and swing. In addition, the quadrature coupling topology is reused as an oscillation detector for dynamic bias control to further decrease power consumption of oscillation cores. A proto-type of the proposed QVCO is designed and fabricated in a 40-nm CMOS process. Measurement results indicate that the QVCO achieves a phase noise of −118.6dBc/Hz@1 MHz at the carrier of 1.575 GHz. The power consumption of the proposed QVCO is only 1.32 mW under the supply voltage of 0.6 V.

A broadband GaAs pHEMT low noise driving amplifier with current reuse and self-biasing technique

A K/Ka-band two-stage low noise driving amplifier using a 0.15 μm GaAs pHEMT for low noise technology is designed and fabricated. In order to achieve broadband driving capability with low power consumption, current reuse technique is adopted to feed both transistors with the same DC power supply, which theoretically cuts the total current consumption in half. In addition, self-biasing technique is utilized to minimize both external power supply pads and chip footprint, which reduces the number of supply pads to a minimum of two (1 power pad and 1 ground pad). The circuit topology analysis and design procedures are also presented with an emphasis on noise figure and P1dB optimization. The low noise driving amplifier demonstrates a − 3 dB bandwidth of wider than 11 GHz, a power gain of 17 dB, an in-band mean noise figure of 2.2 dB and an in-band mean output P1dB of 6 dBm. The DC power consumption is 9.1 mA@3.3 V power supply. The chip size is 1 mm × 1.5 mm with only 1 external DC feed pad (3.3 V) and 1 ground pad (0 V). With the performance comparable to typical two-stage dual-bias low noise driving amplifier counterparts, the proposed MMIC is more attractive to chip/system users in volume-limited and power-contrained applications.

A low phase noise quadrature VCO using superharmonic injection, current reuse, and negative resistance techniques in CMOS technology

In this article, a low phase noise quadrature VCO (QVCO) is proposed, which uses superharmonic injection and current reuse techniques to reduce phase-noise and power consumption. The LC tank circuit quality factor is improved, using a negative resistance. PMOS transistors have also been used instead of NMOS transistors. As a result of these modifications, further phase noise reduction is achieved. The QVCO consists of a VCO operating at 2ω0 (twice the operating frequency) injecting its output signal into the common source nodes of two other oscillators operating at ω0. Using this superharmonic injection technique, in addition to phase noise reduction, the chance of injection pulling caused by powerful PA signals is reduced. Also, the current reuse technique automatically adapts its voltage to the requirement of the supplied stages, therefore, it is not limiting the VCO output swing. Designed for the 900 MHz band and simulated in a 0.18 µm CMOS technology with 1.8 V power supply, the circuit achieves a phase noise of − 141.5 dBc/Hz at 1 MHz offset frequency, while consuming 12.8 mW power. The proposed circuit is compared with several re-simulated previously published work. The comparison shows 17.5 dB reduction in phase noise compared to conventional P-QVCO, while consuming the same amount of power.

A wideband design analysis of LNA utilizing complimentary common gate stage with mutually coupled common source stage

This paper presents a wideband low noise amplifier (LNA) which consist cascade of two stages. First stage, a complimentary common gate (CCG) stage is utilized to consume low power and low chip area while second stage is the mutually coupled common source (CS) stage used to generate high gain at high frequency. The concept of current reuse technique is used in CCG stage to save the dc power. While for the objective of low chip area, mutually coupled inductors are used, mathematically equivalent to a transformer. CCG stage provides high gain at low frequency. A frequency dependent load is generated by mutually coupled CS stage to transfer this gain at high frequency and then this load is transferred to the CCG stage using load transformation technique. This help a lot in achieving wide band input matching hence low noise figure (NF). Proposed LNA is verified mathematically and simulated in 90-nm CMOS process. The measured 3-dB bandwidth is 4.7–14.7 GHz with maximum voltage gain of 17.2 dB, minimum NF of 1.8 dB and S11 < − 10.3 dB. Maximum available power gain (GA) is 11.9 dB and maximum operating power gain is 11.4 dB at frequency of 13.2 GHz.

A 0.5–6.5-GHz 3.9-dB NF 7.2-mW active down-conversion mixer in 65-nm CMOS

In the paper, a broadband CMOS active down-conversion mixer is presented. Specifically, a noise-canceling transconductor is developed to reduce the noise figure of the mixer. The current-reuse technique applied to the developed transconductor by stacked nMOS/pMOS architecture not only saves power consumption of the circuit, but also reduces the undesirable parasitics. Moreover, two passive [Formula: see text]-type networks are exploited to absorb internal parasitics of the circuit and guarantee broadband operation. Implemented in an advanced 65-nm CMOS process, post-simulations show that, driven by 0 dBm sinusoidal LO signal, the proposed mixer provides a maximal conversion gain of 15 dB and a NF of 3.9–4.9 dB across RF input frequency range of 0.5–6.5 GHz. The IIP3 and IP1dB of 3.1 and −6.9 dBm are obtained, respectively. The mixer core consumes 7.2 mW from a 1 V supply.

Two‐stage current‐reused variable‐gain low‐noise amplifier for X‐band receivers in 65 nm complementary metal oxide semiconductor technology

In this study, a variable gain low noise amplifier (VG-LNA) working at X band is designed and simulated in 65 nm complementary metal oxide semiconductor technology. A two-stage structure is used in the proposed VG-LNA. Besides, the current-reused technique causes a higher gain without consuming extra power. As an on-chip voltage ( V cnt ) is changed, the gain continuously and almost linearly varies. The highest gain is 27.8 dB that can be reduced to 8.3 dB almost linearly and continuously as the control voltage is increased. The lowest value of S11 is −28.2 dB at 10 GHz. Also, NF is <2.75 dB at the operating frequency range; while NF min = 1.8 dB. The highest value of third-order intercept point is 2.03 dBm that always remain larger than −10.1 dBm. The basic advantage of this structure in comparison with other similar works is that not only the key parameters remain fixed with reduction of gain, but also the operation range of V cnt is widened from 0.3 V to V dd in order to extend the gain control range to 19.5 dB. Moreover, these results are achieved in a situation that the proposed VG-LNA draws only 3.9 mA from a 1.2 V.

A wideband noise cancelling balun LNA employing current reuse technique

A balun inductorless wideband low noise amplifier (LNA) with active loads is proposed for multi-standard radio applications. The noise cancelling and current reuse techniques are combined to mitigate the need for high power consumption in conventional balun LNAs. This adds a degree of freedom for transconductance of common gate stage (gmCG). As a result, lower gmCG without degrading the input matching, allows a large scaling factor for common source (CS) stage in noise cancelling technique. Post-layout simulation results of the proposed LNA circuit in a 180 nm RF CMOS process show voltage gain of 20.2 dB, −3 dB bandwidth from 600 MHz to 3.15 GHz. The minimum NF is 2.37 dB with input return loss (S11) better than −13 dB in all frequency range and third input intercept point (IIP3) is −2.1 dBm. The circuit dissipates 6 mW from 1.5 V DC supply with an active area of 0.026 mm2.

An inductorless active mixer using stacked nMOS/pMOS configuration and LO shaping technique

In this paper, a CMOS active down-conversion mixer is presented for wideband applications. Specifically, a LO generation chain is suggested to convert AC LO signal to shaped trapezoid burst, which reduces the sinusoidal LO power level requirement by the mixer. The current-reuse technique by stacked nMOS/pMOS architecture is used to save the power consumption of the circuit. Moreover, this complementary configuration is also employed to compensate second-order nonlinearity of the circuit. Implemented in a 0.18-[Formula: see text]m CMOS process, post-simulations show that, driven by only −10 dBm sinusoidal LO signal, the proposed inductorless mixer provides a maximal conversion gain of 15.7 dB and a noise figure (NF) of 9.1–12 dB across RF input frequency range 0.5–1.6 GHz. The IIP3 and IP1dB of 3.5 dBm and −4.8 dBm are obtained, respectively. The mixer core only consumes 3.6 mW from a 1.8-V supply.

A current-reuse biomedical amplifier with a NEF &lt; 1

Noise Efficiency Factor (NEF) is the most employed figure of merit to compare different low-noise biomedical signal amplifiers, taking into account current consumption, noise, or bandwidth trade-offs. A small NEF means a more efficient amplifier, and was assumed to be always NEF > 1 (an ideally efficient single BJT amplifier). In this work current-reuse technique will be utilized to exceed this limit in a very efficient CMOS amplifier. A micro-power, ultra-low-noise amplifier, aimed at electro-neuro-graph signal recording in a specific single-channel implantable medical device, is presented. The circuit is powered with a standard medical grade 3.6 V(nom) secondary battery. The amplifier input stage stacks twelve differential pairs to maximize current-reuse. The differential pair stacking technique is very efficient: allows most of the energy to be dissipated in the input transistors that amplify and not in mirror or bias transistors, and allows also the input transistors to operate with a reduced VDS just above saturation. The amplifier was implemented in a 0.6 μm technology, it has a total gain of almost 80 dB, with a 4 kHz bandwidth. The measured input referred noise is 4.5 nV/Hz1/2@1 kHz, and 330 nVrms in the band of interest, with a total current consumption of only 16.5 μA from the battery (including all the 4 stages and the auxiliary circuits). The measured NEF is only 0.84, below the classic NEF = 1 limit.

Design of UWB low noise amplifier using noise-canceling and current-reused techniques

In this paper, an ultra-wideband (UWB) low-noise amplifier (LNA) with low noise-figure (NF) and high power gain (S21) using 0.18-um CMOS technology is presented, which operates from 3GHz up to 12GHz. In the proposed amplifier, a combination of noise-canceling and current-reused technique is used to reduce noise and power consumption, while the gain and the linearity will be improved. The dominant noise source is canceled by the noise-canceling technique. In addition, good input impedance matching is achieved with using both the inductive source degeneration and resistive feedback techniques. The proposed LNA achieves high and flat S21 of 19.24–20.24dB and S11 less than −10dB for frequencies 3–12GHz. Additionally, flat NF of 1.72–1.99dB is achieved for the frequency range of 3–12GHz. Furthermore, the IIP3 is −5.5dBm, power consumptions at 1.8-V supply voltage is 23.23mW and the core layout size is 857.06µm×770.72µm.

A Very Low Power Quadrature VCO with Modified Current-Reuse and Back-Gate Coupling Topology

In this paper, a very low power modified current-reused quadrature voltage-controlled oscillator (QVCO) is proposed with the back-gate coupling technique for the quadrature signal generation. By stacking switching transistors in series like a cascode, the modified current-reused QVCO can be constructed in a totem-pole manner to reuse the dc biasing current and lower the power consumption. By utilizing the back-gates of switching transistors as coupling terminals to achieve the quadrature outputs, the back-gate coupled QVCO improves the phase noise and reduces the power consumption compared to the conventional coupling transistor based topology. Together with the modified current-reuse and back-gate coupling techniques, the proposed QVCO can operate at reduced supply voltage and power consumption while maintaining remarkable circuit performance in terms of low phase noise and wide tuning range. With a dc power of 1.6[Formula: see text]mW under a 0.8[Formula: see text]V supply voltage, the simulation results show the tuning range of the QVCO is from 2.36 to 3.04[Formula: see text]GHz as the tuning voltage is varied from 0.8 to 0.0[Formula: see text]V. The phase noise is [Formula: see text]118.3[Formula: see text]dBc/Hz at 1[Formula: see text]MHz offset frequency from the carrier frequency of 2.36[Formula: see text]GHz and the corresponding figure-of-merit of the QVCO is [Formula: see text]183.7[Formula: see text]dBc/Hz.

A Flexible Continuous-Time $\Delta \Sigma $ ADC With Programmable Bandwidth Supporting Low-Pass and Complex Bandpass Architectures

A flexible continuous-time $\Delta \Sigma $ modulator that supports both low-pass and complex bandpass (CBP) architectures with the programmable bandwidths of 5 and 10 MHz is presented. By utilizing flexibility into both architectural level and core building blocks, scalable power consumption is obtained for each mode with desired performance. An amplifier topology with active feedforward, antipole splitting, and current reuse techniques is proposed for effective power reduction. A prototyped $\Delta \Sigma $ modulator in a 65-nm CMOS achieves a 65.1-/62.2-dB peak signal-to-noise-plus-distortion ratio (SNDR) with a 5-/10-MHz bandwidth in the LP architecture and a 62.9-/64.1-dB SNDR over a 5-/10-MHz signal band with a tunable center frequency of 4–6 MHz in the CBP architecture, respectively. The figure of merit is 0.21/0.23/0.36/0.24 pJ/conversion step for each mode with a power consumption of 3.1/4.8/4.2/6.3 mW by a 1.2 V supply voltage. The dynamic range is 73/65.8/74.3/74.2 dB. The active area is 0.39 mm2.