Current-reuse Structure Research Articles

CMOS voltage‐controlled oscillator using inductive dual‐balance source degeneration

This study reports a voltage-controlled oscillator (VCO) implemented in a 0.18-μm CMOS process. By utilizing an inductive dual-balance source degeneration (IDSD) technique with a current-reused structure, the proposed VCO improves the phase noise and the power dissipation. The measured output frequency operates at 2.91–3.07 GHz by adjusting a control voltage from 0 to 1.1 V. The measured phase noise of the carrier of 2.94 GHz is −117.44 and −138.34 dBc/Hz at 1- and 10-MHz offsets, respectively. The proposed VCO core consumes 2.38 mW from a supply voltage of 1.1 V. The figures-of-merits (FOMs) of the proposed VCO at 1- and 10-MHz offsets are −183.04 dBc/Hz and −183.94 dBc/Hz, respectively.

A C-band low-power sub-1volt current-reused multiphase oscillator

A new sub-1V and low power multiphase voltage-controlled oscillator (QVCO) with current-reused structure is proposed. The proposed core oscillator consists of two N-metal oxide semiconductor (NMOS) and P-metal oxide semiconductor (PMOS) transistors and an additional NMOS-only cross-coupled pair that enhances the effective negative transconductance and facilities the start-up condition at sub-1V supply voltages in modern nm CMOS technologies. In the proposed coupling scheme, the gate of cross-coupled transistors is used for coupling in an ‘in-phase−anti-phase’ manner. Parallel capacitors to the drain-source of transistors have been used for further enhancement of effective transconductance and thus lower power consumption; though the increase of parallel capacitors reduces the tuning range, indicating a trade-off in the proposed QVCO. The proposed quadrature oscillator is designed and simulated in a standard 0.18 μm RF-CMOS technology. The results of the simulation show that the QVCO has a 9% tuning range from 5.35 GHz to 5.88 GHz, and the phase noise is −119.6 dBc/Hz at 1-MHz offset from the 5.7 GHz carrier while consumes only 1.4 mW from a 0.85-V supply voltage; yielding an excellent figure-of-merit (FOM) of −193.3 dBc that is amongst the best FOMs. Several Monte Carlo and PVT analyses verify the robust performance of the QVCO.

Concurrent Dual-Band Inverter-Based Low Noise Amplifier (LNA) for WLAN Applications

low noise amplifier (LNA); concurrent; dual-band; inverter-basedIn this paper, a two-stage concurrent dual-band low noise amplifier (DB-LNA) operating at 2.4/5.2-GHz is presented for Wireless Local Area Network (WLAN) applications. The current-reused structure using resistive shunt-shunt feedback is employed to reduce power dissipation and achieve a wide frequency band from DC to-5.5-GHz in the inverter-based LNA. The second inverter-based stage is employed to increase the gain and obtain a flat gain over the frequency band. An LC network is also inserted at the proposed circuit output to shape the dual-band frequency response. The proposed concurrent DB-LNA is designed by RF-TSMC 0.18-µm CMOS technology, which consumes 10.8 mW from a power supply of 1.5 V. The simulation results show that the proposed DB-LNA achieves a direct power gain (S 21 ) of 13.7/14.1 dB, a noise figure (NF) of 4.2/4.6 dB, and an input return loss (S 11 ) of −12.9/−14.6 dBm at the 2.4/5.2-GHz bands.

Design of 0.13 µm low power CMOS subharmonic mixer for DCR applications

ABSTRACT This paper presents a design of 2.4 GHz folded subharmonic active mixer in TSMC 130 nm CMOS process for direct conversion receiver (DCR). To achieve the low supply voltage, the folded topology is adopted for the proposed subharmonic mixer. The complementary current reuse structure is used as RF transconductance stage where the biasing for the PMOS and NMOS transistors are self-biased by a resistor to support high conversion gain at low supply voltage. Frequency doubling operation is done by the mixing core which is driven by a quadrature local oscillator (LO) signals. The proposed mixer is designed and simulated using ADS (Advanced Design System) simulator with Cadence software. It produces 10.5 dB conversion gain, a single sideband) noise figure of 9.5 dB, 2 LO-to-RF isolation of 53 dB, LO-to-RF isolation of 117 dB, RF-to-IF isolation of 55 dB and IIP3 of −7.5 dBm. The quadrature LO subharmonic mixer consumes 824μW power from a supply voltage of 0.8 V. The proposed mixer is compared with existing subharmonic mixers. The comparison shows the proposed subharmonic mixer gives a good Figure of Merit.

Optimum design of a new ultra-wideband LNA using heuristic multiobjective optimization

This paper presents an optimum design of an ultra-wideband (UWB) 2.5–10.5-GHz low-noise amplifier (LNA) in 180-nm and 65-nm radiofrequency (RF)-complementary metal–oxide–semiconductor (CMOS) technology. A novel input matching network employing resistive–inductive feedback and a noise-canceling technique is proposed to achieve broadband matching as well as a low noise figure (NF). Moreover, a current-reused structure and the inductive peaking technique are applied in the proposed LNA to reduce its power consumption and provide high, flat gain. The proposed UWB-LNA is optimized using heuristic multiobjective optimization based on inclined planes system optimization (IPO) and particle swarm optimization (PSO) as simulation-based evolutionary techniques. The proposed UWB-LNA is designed and simulated using HSPICE and Cadence Spectre RF. The postlayout simulation results show an input return loss (S11) of less than −10 dB, a flat power gain (S21) of 13.2 ± 0.5 and 14 ± 0.5 dB, and an NF below 5 and 2.5 dB over the whole UWB band when implemented in 180-nm and 65-nm CMOS technology, respectively. The UWB-LNA consumes 7.2 and 9.5 mW from a 1.8-V power supply when implemented in 180-nm and 65-nm CMOS technology, respectively.

A 2.99 dB NF 15.6 dB Gain 3-10GHz Ultra-wideband low-noise amplifier for UWB systems in 65 nm CMOS

A low noise figure (NF) and high power gain (S21) 3–10 GHz ultra-wideband (UWB) low noise amplifier (LNA) in 65 nm CMOS technology is proposed for UWB system which has a high figure of merit. A shunt–shunt resistive feedback technique is used to achieve wideband input impedance matching. A differential current-reused structure is used to achieve high common noise suppression and low power consumption. The implemented LNA achieves a high and flat aS21 of 15.6 ± 1.07 dB with an input return loss (S11) which is better than − 8.7 dB and a low NF of 2.99 ± 0.18 dB at frequencies of 3–10 GHz. The measured input third-order intermodulation point (IIP3) is − 5.7 dBm at 6 GHz.

A current-reuse dual-channel bio-signal amplifier for WBAN nodes

This paper presents a dual-channel low-noise bio-signal amplifier for the low-power wireless body area network (WBAN) nodes. A dual-channel three-input current-reuse (DTCR) structure is proposed to optimize the noise performance of amplifier. The chopper-stabilized technique is employed to reduce 1/f noise and the offset voltage. Moreover, a high input impedance is achieved by using the pre-charge technique. In addition, a DC offset canceling loop is employed to suppress the electrode offset. The proposed amplifier is implemented in a standard 0.18 μm CMOS process with an active area of about 0.68 × 0.73 mm2. The experimental results demonstrate that an input referred noise of 1.12 μVrms has been achieved over a bandwidth from 0.35 Hz to 150 Hz. The total power consumption of each channel is about 1.44 μW at the supply voltage of 1.2 V. And the amplifier achieves an input impedance of about 200 MΩ, a CMRR of 111 dB at 50 Hz and a PSRR of 87.5 dB at 50 Hz.

Low-Flicker-Noise and High-Gain Mixer Using a Dynamic Current-Bleeding Technique

This letter presents a low-flicker-noise and high-gain folded-type mixer using current-reuse and dynamic current-bleeding (DCB) techniques. The current-reuse structure allows the use of the current-bleeding (CB) technique in the folded-type mixer. A local oscillator signal at the IF port dynamically switches the CB circuit, which results in a low flicker noise and high gain. Because the DCB circuit is composed of a common-mode negative-feedback structure, it stabilizes the linearity and noise figure (NF) for process variation and mismatch. The measurements show a double-sideband NF of 8.2 dB at an IF of 10 kHz and a conversion gain of 24.1 dB at 2.1 GHz, while the mixer consumes 2.1 mW from a supply voltage of 1.2 V.

An Ultra-Low-Power Wideband Inductorless CMOS LNA With Tunable Active Shunt-Feedback

This work presents and analyzes the design of a 1-V ultra-low power, compact, and wideband low-noise amplifier (LNA). The proposed LNA uses common-gate (CG) NMOS and PMOS transistors as input devices in a complementary current-reuse structure. Low power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor to improve the current efficiency of the LNA. A forward body biasing (FBB) scheme is exploited to tune the feedback coefficient. The complementary characteristics of the input stage leads to partial second-order distortion cancellation. The proposed inductorless LNA is implemented in an IBM 0.13-μm 1P8M CMOS technology and occupies only 0.0052 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . The measured LNA has a 12.3-dB gain 4.9-dB minimum noise figure (NF) input referred third-order intercept point (IIP3) of -10 dBm and 0.1-2.2-GHz bandwidth (BW), while consuming only 400 μA from a 1-V supply.

A High Gain Broadband Low Noise Amplifier for Wireless Networks

In this paper, a high gain broadband low noise amplifier with flat power gain is designed for using in the wireless systems in frequency range of 2-5.5 GHz. This LNA is designed employing two pHEMT devices which are in cascode while using current reuse structure. The low noise amplifier which is unconditionally stable in the over frequency range of 2-5.5 GHz, is achieved to have maximum power gain of 28.28 dB at 2.25 GHz. Minimum noise figure of the LNA is 0.939 dB. Maximum of input return loss, output return loss and reverse isolation are less than - 10.15 dB, less than - 10.53 dB and below - 39.18, respectively. The LNA consumes DC power of 54.92 mw. The figure of merit (FOM) of proposed broadband LNA was calculated that shows good improvement compared with other works.

A Low Power High Gain CMOS LNA with Multiple-Feedback Network for Low Voltage UWB Receiver

In this paper, a high gain low voltage low power Complementary Metal Oxide Semiconductor (CMOS) Low-noise Amplifier (LNA) using Chartered 0.18[Formula: see text][Formula: see text]m CMOS process for Ultra-wideband (UWB) receiver applications is presented. A novel multiple-feedback network constructed by the shunt feedback resistor with a transformer is adopted to realize desirable bandwidth extension and less chip area occupation in the common-source stage. All the cascaded transistors are configured by current-reuse structure and adjusted by forward body bias technique to further reduce supply voltage and power dissipation. The post-layout simulation results demonstrate that the proposed 3.4–10.1[Formula: see text]GHz UWB LNA accomplishes a maximum gain of 14.26[Formula: see text]dB with only 2.33[Formula: see text]mW power consumption at 0.8[Formula: see text]V supply voltage, while Noise Figure (NF) is 1.49–3.41[Formula: see text]dB and the chip area is 0.46[Formula: see text]mm2 including test pads (core area is 0.23[Formula: see text]mm2).

Short Channel Output Conductance Enhancement Through Forward Body Biasing to Realize a 0.5 V 250 0.6–4.2 GHz Current-Reuse CMOS LNA

This work examines the use of a forward body biasing (FBB) scheme to mitigate output conductance degradation due to short channel effects in ultra-low voltage (ULV) circuits with no additional power consumption. It is shown that FBB boosts the output resistance of a transistor such that the intrinsic gain reduction due to low-supply voltages can be compensated. This technique is then used to implement a low-noise amplifier (LNA) tailored for ultra-low power (ULP) and ULV applications. The proposed LNA uses common-gate (CG) NMOS transistors as input devices in a complementary current-reuse structure. Low-power input matching is achieved by employing an active shunt-feedback architecture while the current of the feedback stage is also reused by the input transistor. Moreover, a separate FBB scheme is exploited to tune the feedback coefficient. An inductive $g_m$ -boosting technique is used to increase the bandwidth of the LNA without additional power consumption. The proposed LNA is implemented in an IBM $0.13 \upmu \text{m}$ 1P8M CMOS technology and occupies $0.39 \text{mm}^2$ . The measured LNA has a 14 dB gain, 4 dB minimum noise figure, IIP3 of $-10 \text{dBm}$ , and 0.6–4.2 GHz bandwidth, while consuming only $500 \upmu$ A from a 0.5 V supply. The LNA operates with supplies as low as 0.4 V while maintaining good performance.

Design of low power CMOS LC VCO for direct conversion transceiver

A low power 1.2 GHz LC differential voltage-controll ed oscillator (VCO) is designed for a direct conversion transceiver in 130 nm CMOS processes. It consists of a complementary current reuse structure and LC tank circuit. To produce a good tuning range and reduce losses in the tank circuit, modied inversion mode PMOS varactors and an on-chip inductor are designed with a better quality factor. The icker noise is reduced by the PMOS tail current source connected in parallel with the capacitance. The 1.2 GHz LC VCO achieves a phase noise value of {132 dBc/Hz at 1 MHz offset and the tuning range of the oscillator is from 1.128 to 1.27 GHz for the control voltage, tuning from 0 to 1.5 V. It dissipates 245 W power at 0.8 V supply voltage and thegure of merit is calculated as {199.7 dBc/Hz.

A Low Power LNA-Phase Shifter With Vector Sum Method for 60 GHz Beamforming Receiver

Taking into consideration the limitations of the conventional vector sum phase shifter (VSPS), a low power LNA-PS is proposed for a 60 GHz beamforming receiver using a 65 nm CMOS process. By developing a low loss 90 $^{\circ}$ PS that integrates the HPF into the LPF with a low loss SPST switch and a power efficient vector adder using a current reuse structure, the proposed LNA-PS shows the gain of 24 dB, the highest among the LNA-PSs developed to date, with very small power consumption of 16 mW. The total size including the pads is only 1.3 ${\rm mm}^{2}$ .

0.5 V 5.8 GHz highly linear current-reuse voltage-controlled oscillator with back-gate tuning technique

In this paper, we present a voltage-controlled oscillator (VCO), which achieves highly linear frequency tuning under a low supply voltage of 0.5 V. To obtain the linear frequency tuning of a VCO, the high linearity of the threshold voltage of a varactor versus its back-gate voltage is utilized. This enables the linear capacitance tuning of the varactor; thus, a highly linear VCO can be achieved. In addition, to decrease the power consumption of the VCO, a current-reuse structure is employed as a cross-coupled pair. The proposed VCO was fabricated using a 65 nm Si complementary metal oxide semiconductor (CMOS) process. It shows the ratio of the maximum VCO gain (KVCO) to the minimum one to be 1.28. The dc power consumption is 0.33 mW at a supply voltage of 0.5 V. The measured phase noise at 10 MHz offset is −123 dBc/Hz at an output frequency of 5.8 GHz.

Optimal Design of Low Power CMOS Power Amplifier Using Particle Swarm Optimization Technique

A low voltage 2.4 GHz CMOS power amplifier for wireless personal area network (WPAN) applications is presented in TSMC 0.13 $$\upmu $$μm CMOS process. It consists of driver and power amplifier stages which are connected in current reuse structure. The driver amplifier has push pull inverter configuration. The power amplifier is the common source amplifier. These two stages are biased in class AB mode. For optimizing out-of-band emissions, the proposed power amplifier is linearized by RF predistortion technique. For efficient power amplifier, the design parameters are needed to be optimized using particle swarm optimization technique. The optimized power amplifier achieves 0 dBm output power, 34.06 % PAE, 18 dB power gain at 2.4 GHz frequency. It consumes 2.95 mW power at a supply voltage of 1.2 V.

Design of low power CMOS ultra wide band low noise amplifier using noise canceling technique

This paper presents a design of a low power CMOS ultra-wideband (UWB) low noise amplifier (LNA) using a noise canceling technique with the TSMC 0.18μm RF CMOS process. The proposed UWB LNA employs a current-reused structure to decrease the total power consumption instead of using a cascade stage. This structure spends the same DC current for operating two transistors simultaneously. The stagger-tuning technique, which was reported to achieve gain flatness in the required frequency, was adopted to have low and high resonance frequency points over the entire bandwidth from 3.1 to 10.6GHz. The resonance points were set in 3GHz and 10GHz to provide enough gain flatness and return loss. In addition, the noise canceling technique was used to cancel the dominant noise source, which is generated by the first transistor. The simulation results show a flat gain (S21>10dB) with a good input impedance matching less than –10dB and a minimum noise figure of 2.9dB over the entire band. The proposed UWB LNA consumed 15.2mW from a 1.8V power supply.

A Back-Gate Coupling Quadrature Voltage-Control Oscillator Embedded With Self Body-Bias Schema

A quadrature voltage-controlled oscillator was designed with back-gate coupling and embedded self body-biasing and implemented with the TSMC 0.18 μm 1P6M CMOS technology. Without using any extra negative bias-pin in the current-reuse structure, this embedded body-bias schema makes the switching transistors become forward body-biased in the duration of turn-on. It is not only beneficial for low-voltage operation, but also achieves a high oscillating output power (-2.5 dBm) with less supply power (2.5 mW). The percentage of frequency tuning range is 17.5% (from 4.60 to 5.48 GHz). The phase noise is -114 dBc/Hz at 1-MHz offset from the carrier frequency of 5.48 GHz.

Processing Chip for Thin Film Bulk Acoustic Resonator Mass Sensor

Aimed at portable application, a new integrated process chip for thin film bulk acoustic resonator (FBAR) mass sensor is proposed and verified with 0.18 um CMOS processing in this paper. The longitudinal mode FBAR with back-etched structure is fabricated, which has resonant frequency 1.878 GHz and Q factor 1200. The FBAR oscillator, based on the current-reuse structure, is designed with Modified Butterworth Van Dyke (MBVD) model. The result shows that the FBAR oscillator operates at 1.878 GHz with a phase noise of -107 dBc/Hz and -135 dBc/Hz at 10 KHz and 100 KHz frequency offset, respectively. The whole process chip size with pads is 1300 µm × 950 µm. The FBAR and process chip are bonded together to sense tiny mass. The measurement results show that this chip precision is 1 KHz with the FBAR frequency gap from 25 kHz to 25MHz.

Design of Low Power CMOS LNA with Current-Reused and Notch Filter Topology for DS-UWB Application

This paper presents the design of a low power LNA with second stage that uses a notch filter for DS-UWB application. The LNA employs a current reuse structure to reduce the power consumption and an active second order notch filter to produce band rejection in the 5 - 6 GHz frequency band. The input reflection coefficient S11 and output reflection S22 are both less than –10 dB. The maximum power gain S21 is 15 dB while the maximum rejection ratio is over –10 dB at 4.8 GHz. The minimum noise figure is 5 dB. The input referred third-order intercept point (IIP3) is –7 dBm at 6 GHz. The power consumption is 6.4 mW from a 1-V power supply.