Current-mode Driver Research Articles

A 28/56 Gb/s NRZ/PAM-4 Dual-Mode Transmitter with Eye-Opening Enhancement in 28 nm CMOS

This paper presents a non-return-to-zero (NRZ)/4-level pulse amplitude modulation (PAM-4) dual-mode wireline transmitter with an eye-opening enhancement technique to improve horizontal eye-opening. With the eye-enhancement pulse generator and the auxiliary pull-up device in the tail-less current-mode driver, the worst-case horizontal eye-opening increased by 30% in the PAM-4 eye diagram. The power efficiency of the NRZ mode was also improved by completely turning off the LSB path in the differential data path, resulting in only a 31% power efficiency degradation, which is far lower than that of the prior dual-mode transmitters. Fabricated in 28 nm CMOS, the transmitter achieves power efficiency of 1.4 pJ/bit at 56 Gb/s in PAM-4 mode and 1.84 pJ/bit at 28 Gb/s in NRZ mode, respectively.

An Automated Framework for Variability Analysis for Integrated Circuits Using Metaheuristics

This work aims to analyze the variability of integrated circuits and systems. An automated framework is presented for variability analysis that exploits the metaheuristic optimization techniques. The efficacy of the proposed approach is demonstrated by two case studies- one is the estimation of variability in phase noise in RF CMOS LC tank oscillators (frequency domain analysis) and other being the estimation of variability in the differential output signal of a current mode driver (time-domain analysis). The proposed approach is investigated and validated by comparing the results from the traditional Monte-Carlo simulations and the Ordinary-Least Squares based Polynomial Chaos Expansion. A significant gain in the computational time is reported while maintaining accuracy in the results. The proposed methodology is not just limited to variability analysis applications but also can be used to solve the circuit optimization problems.

An 87% Power-Efficiency Hybrid of Voltage- and Current-Mode Line Driver with an Adaptive Amplitude Tuning

This brief presents a hybrid of voltage- and current-mode line drivers for the turbo controller area network (CAN). The current-mode scheme prevents signal attenuation caused by source termination resistors, and it enhances signal power efficiency. On top of that, an adaptive amplitude tuning is implemented to mitigate non-linearity and closed-loop gain variations against load impedance variations. The proposed line driver achieves 87.0% power-efficiency and total harmonic distortion, plus noise (THD+N) of −49.0 dB at an input frequency of 40 MHz and output swing of 2.8 VPP differential. The adaptive amplitude tuning allows load impedance variations from 80 Ω to 160 Ω. The total power consumption is 37.6 mW with a 1.8 V supply voltage in 180 nm CMOS, and it occupies 0.377 mm2.

A Duo-Binary Transceiver With Time-Based Receiver and Voltage-Mode Time-Interleaved Mixing Transmitter for DRAM Interface

A duo-binary signaling has been applied to both transmitter and receiver for high-speed low-power DRAM interface. The transmitter consists of a half-rate voltage-mode time-interleaved mixing duo-binary driver and a 2-tap feed-forward equalizer. The voltage-mode driver is used in this brief, because it generates more linear output voltage than the current-mode driver for the duo-binary signaling at low supply voltage. A time-based receiver is used for high-speed operation at low supply voltage. A 1-tap look-ahead decision-feedback equalizer scheme was applied to the time-based receiver for the duo-binary decoding operation. The test chip fabricated in a 28 nm low-power CMOS process gives the energy efficiency of 0.41 pJ/b at 12 Gb/s with a 25 cm-long FR-4 micro-strip line and the supply voltage of 0.75V.

A Differential Push-Pull Voltage Mode VCSEL Driver in 65-nm CMOS

Improving power-conversion efficiency (PCE) of VCSEL drivers is paramount to improve the overall energy efficiency of the entire optical link for high-performance computing and datacenters. VCSEL diodes are normally driven single-ended with pseudo-differential current-mode drivers to maintain signal integrity. However, such conventional drivers consume significant power and are often unable to compensate for supply switching noise due to package parasitics at high data-rates. We propose a differential push-pull voltage-mode VCSEL driver to mitigate bondwire parasitics, reduce power consumption, and leverage CMOS process scaling to its maximum advantage. A proof-of-concept prototype in 65-nm CMOS process achieves the highest ever-reported PCE of 18.7 % for VCSEL drivers when normalized to VCSEL slope efficiency. It uses an asymmetric 3-tap rise and fall-based pre-emphasis to achieve a total energy/bit of 1.52 pJ/b at 16 Gb/s with an average optical power output of 1.34 dBm, OMA of 2.1 dBm, and extinction ratio of 5.92 dB.

Fast Analysis of Time Interval Error in Current-Mode Drivers

An efficient approach for modeling of time interval error (TIE) due to noise in power delivery networks (PDNs), for current-mode (CM) driver circuits, is presented. Semianalytical expressions relating the PDN noise and TIE are developed based on midpoint delays of the rising and falling edges of the differential signal. The validating examples with CM driver circuits designed in various technologies comparing both the proposed and conventional approaches demonstrate a significant speedup using the proposed approach.

Variability Analysis of Stochastic Parameters on the Electrical Performance of On-Chip Current-Mode Interconnect System

ABSTRACTCurrent-mode signalling scheme is one of the prominent solutions for high-speed and high data rate communication in global on-chip interconnects. Advancements in nanofabrication processes and housing of billions of transistors on a single silicon chip have made process-induced variations in transistors and interconnects quite significant. Analysis of parameter variations has become an important step in predicting the reliability and addressing various electronic circuit design issues in nanoscale regimes. The present paper evaluates the stochastic parameters variability on the electrical performance of on-chip current-mode interconnect system. Both transistor and interconnect variability effects are analyzed. Interconnect is modelled by an equivalent distributed line model and is driven by a current-mode driver. The impact of variability is assessed via parametric, process corner and Monte–Carlo analyses. The variability analysis is carried out for single as well as coupled 2-Line, 3-Line and 5-Line interconnect structures. Furthermore, the impact of individual process parameter variability in current-mode interconnect system has been investigated using statistical techniques namely Taguchi design of simulation scheme, ANOVA and Rank table.

A 3 Gb/s multichannel transceiver in 65 nm CMOS technology

This paper describes a 65 nm 16-bit parallel transceiver IP macro, whose rate is 3 Gb/s with a 5 pF load including the HBM 2000 V ESD protection. Equalizers and clock data recovery modules, CRC checkers and 8 b/10 b encoders are not added in the design for reducing the latency, and the whole latency is 7 ns without cables. Since the transceiver has many robust features including a process, voltage and temperature independent phase-locked loop with calibrations, the low skew differential clock tree, and a stable current mode driver with common mode feedback, the transceiver can work properly at different process corners and extreme temperatures, and also can tolerate 20% power supply variations. The transceiver can be applied for the interface of sub-100 nm high performance processors, which require low latency and high stability. The transceiver shows a bitter error ratio of less than 10−15 at 3 Gbps.

A 4.8-mW/Gb/s 9.6-Gb/s 5 <inline-formula> <tex-math notation="TeX">$+$</tex-math></inline-formula> 1-Lane Source-Synchronous Transmitter in 65-nm Bulk CMOS

A low-jitter and low-power source-synchronous serializer/deserializer transmitter (TX) with a data rate of 9.6 Gb/s is presented. The TX consists of five data channels plus one forwarded-clock channel and features a total jitter of 20.39 ps p-p at 10-12 bit error rate. Low jitter is achieved through the use of a phase-locked loop with bandwidth linearization that has a random RMS jitter of 0.66 ps. A global clock distribution network is proposed to minimize the power-supply-induced jitter and the power consumption. The TX transmits preemphasized data through a current-mode logic driver with a four-tap feedforward equalizer. The on-chip output impedance and the signal amplitude can be accurately calibrated by a successive approximation register logic separately. The total power consumption for the 5 +1-lane TX physical core fabricated in 65-nm bulk CMOS running at 9.6 Gb/s is 230 mW or 4.8 mW/Gb/s.

Giga bit per second Differential Scheme for High Speed Interconnect

The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, making off-chip bandwidth an even more critical bottleneck. In order to increase the I/O Bandwidth, some efficient high speed signaling standard must be used which considers the line termination, signal integrity, power dissipation, noise immunity etc In this work, a transmitter has been developed for high speed offchip communication. It consists of low speed input buffer, serializer which converts parallel input data into serial data and a current mode driver which converts the voltage mode input signals into current over the transmission line. Output of 32 low speed input buffers is fed to two serializer, each serializer converting 16 bit parallel data into serial data stream. Output of two serializers is fed to LVDS current mode driver. The serial link technique used in this work is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. Serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical.

40.2: An Improved Differential Signaling Scheme for the Chip‐On‐Glass Application of TFT‐LCD

AbstractAn improved signaling scheme for the intra‐panel interface for the chip‐on‐glass (COG) application is proposed. The proposed signaling scheme adopts a transmitter with the current‐mode driver with shunt termination for an impedance matching on the transmitter and a receiver without termination to eliminate the multiple reflections on the transmitter. It obtains good signal quality on the receiver without additional current consumption. The transmitter for the proposed signaling scheme adopts the current‐mode driver with shunt termination instead of the voltage‐mode driver with series termination resistor for minimizing the effect caused by the process dependency of the circuitry in the transmitter. The receiver for the proposed signaling scheme is equipped with the loss compensator to equalize the channel loss caused by the highly resistive signal line‐on‐glass (LOG) and low channel bandwidth due to open termination on the receiver. The proposed signaling scheme is verified with 9.7‐inch XGA (1024RGB×768) resolution TFT‐LCD module for tablet computer. The proposed signaling scheme achieves the low electromagnetic near‐field radiation from the signal lines by acquiring the good signal integrity on the transmission channel.

Asynchronous Current Mode Serial Communication

An asynchronous high-speed wave-pipelined bit-serial link for on-chip communication is presented as an alternative to standard bit-parallel links. The link employs the differential level encoded dual-rail (LEDR) two-phase asynchronous protocol, avoiding per-bit handshake and eliminating per-bit synchronization, in contrast with synchronous serial links that rely on complex clock recovery. Novel low-power current signaling driver and receiver circuits are presented, enabling high-speed communication at a very low voltage swing over long wires. In contrast, previous methods employed voltage sensing, resulting in higher swing, higher dynamic power, shorter wires or slower operation. The asynchronous current mode driver is designed to support varying data rates, and it eliminates the need for balanced codes and busy toggling that prevent deep discharge. The data cycle time of the link is equal to a single gate delay, enabling 67 Gb/s throughput in 65-nm technology. Wave-pipelining is employed also by the asynchronous SERDES circuits, to enable such high speed operation. The link was SPICE simulated for 65-nm technology, using wire models obtained by a 3-D EM solver. The link incurs lower power and area relative to synchronous and asynchronous bit-parallel communications, and these relative benefits also scale with technology.

Low-power and high-performance techniques in global interconnect signaling

In this article, two accurate and efficient approaches are proposed to optimize the power and delay of global interconnects in VLSI ICs. We modify the conventional buffer insertion and low swing methods for delay and power optimization of various lengths of the global interconnects. As such, we address non-equidistance buffer insertion (NEBI) and current-mode driver and receiver (CMDR) techniques along with our smart optimization procedure. It is shown that the optimized low swing CMDR technique is efficient for global interconnects of the length equal or longer than 5mm, and the improved buffer insertion technique, NEBI, is a perfect choice for the short global interconnects. Additionally, a random search algorithm known as simulated annealing (SA), improved by an intelligent method using a piecewise linear and exponential cost function, is employed for optimization of the power and delay. To this end, we have implemented a smart CAD tool that works interactively with HSPICE to achieve accurate and reliable design results. For verification purposes, several circuits are designed and simulated in 0.25, 0.18, and 0.13μm CMOS technologies. The simulation results verify a significant reduction in the power and delay of global interconnects compared to other methods in the literature.

A Reduced-Swing Voltage-Mode Driver for Low-Power Multi-Gb/s Transmitters

At a lower supply voltage, voltage-mode drivers draw less current than current-mode drivers. In this paper, we newly propose a voltage-mode driver with an additional current path that reduces the output voltage swing without the need for complicated additional circuitry, compared to conventional voltage-mode drivers. The prototype driver is fabriccated in a 0.13-㎛ CMOS technology and used to transmit data streams at the rate of 2.5 Gb/s. Deemphasis is also implemented for the compensation of channel attenuation. With a 1.2-V supply, it dissipates 8.0 ㎃ for a 400-㎷ output voltage swing.

A High-Performance Current-Mode Source Driver IC for Mobile Active Matrix Organic Light Emitting Diode Displays

In this paper, we describe two types of 8-bit current-mode driver ICs with a small area and good performance for applications high accuracy current-mode digital-to-analog converters (DACs), and improved channel-to-channel uniformity for active matrix organic light-emitting diode (AMOLED) displays. One uses the proposed current steering DAC (type A), which is an improved architecture of a binary-weighted DAC, and the other uses a DAC that is a combination of a thermometer-decoded of the DAC and a binary-weighted type. The measured results show that the peak integral nonlinearity (INL) is within ±0.5 the least significant bit (LSB), the peak differential nonlinearity (DNL) is within ±0.5 LSB, and the nonuniformity of output current among channels and chips is within ±0.5 LSB. The size of the driver IC is 15,820 ×1,500 µm2 and the total power consumption of the current-mode driver IC is less than 9 mW when the display has full-white pattern with a luminance of 150 cd/m2. The chip area and power consumption with the proposed current DAC are reduced by 26 and 10%, respectively, compared with those of conventional driver ICs with a fully binary-weighted DAC.

A New Current-Mode Incremental Signaling Scheme With Applications to Gb/s Parallel Links

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A new current-mode incremental signaling (CMIS) scheme and a new fully differential current-integrating receiver for high-speed parallel links are presented. The proposed signaling scheme requires only <formula formulatype="inline"> <tex>$N+1$</tex></formula> physical paths for <formula formulatype="inline"> <tex>$N$</tex></formula> parallel bits. It possesses the intrinsic advantages of current-mode signaling including high data rates, large signal swing, low switching noise injection, and superior signal integrity. The current-integrating receiver consisting of a transimpedance front-end, an integrator, and a sense amplifier with active inductor shunt peaking offers the key advantages of a low and tunable input impedance for channel termination, large bandwidth, and effective suppression of transient noise coupled to the channels. To assess the effectiveness of the proposed signaling scheme and the current-integrating receiver, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10-cm microstrip lines with FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13-<formula formulatype="inline"><tex>$\mu{\hbox {m}}$</tex></formula> 1.2-V CMOS technology and analyzed using <emphasis emphasistype="italic">SpectreRF</emphasis> from Cadence Design Systems with BSIM3.3V device models. Simulation results demonstrate that the proposed CMIS scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5 GB/s. </para>

A Current-Mode Display Driver IC Using Sample-and-Hold Scheme for QVGA Full-Color AMOLED Displays

A display driver IC based on a current-sink driving scheme has been developed for QVGA (240times320), low-temperature poly-silicon (LTPS) active matrix organic light-emitting diodes (AMOLEDs) displays. The current-mode driver IC consists of a source driver block and a controller block. It uses a sample-and-hold scheme in the source driver block. The source driver block has 720 channel outputs, an 8-bit segmented DAC, a pre-charge generation block, and a 64-level gray scale (64 selections out of 256 gray levels for Gamma correction) per channel. The source driver output current ranges from 10 nA to 10 mum. The controller block generates control signals for the source driver and LTPS drivers (emission and scan driver), which are integrated on the panel glass. The current-mode driver IC was fabricated in a 0.18-mum CMOS technology (two poly and four metals) with 5.3-V high-voltage transistor devices

CMOS-based microdisplay with calibrated backplane

A two-stage microdisplay architecture using silicon light emitters and image intensification is presented. A backplane IC implemented in standard 0.18-/spl mu/m CMOS technology incorporating display drivers and an array of avalanche diodes produces a faint optical image, and an image intensifier efficiently amplifies the image to useful luminance levels. This architecture can achieve adequate luminance for projection applications and high energy efficiency. The integrated backplane includes a 360 /spl times/ 200 pixel array with silicon light emitters and 10b precision current-mode driver circuits. The driver circuits can support both silicon light emitters and organic LED (OLED). They employ a self-calibration technique based on the current copier circuit to minimize variation and fixed pattern noise while reducing circuit area by a factor of seven compared to a conventional solution. A circuit technique to improve the retention time of dynamic analog memories is also presented. This technique allows a current copier to retain 10b precision for 500 ms at room temperature.