A New Current-Mode Incremental Signaling Scheme With Applications to Gb/s Parallel Links

Abstract

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> A new current-mode incremental signaling (CMIS) scheme and a new fully differential current-integrating receiver for high-speed parallel links are presented. The proposed signaling scheme requires only <formula formulatype="inline"> <tex>$N+1$</tex></formula> physical paths for <formula formulatype="inline"> <tex>$N$</tex></formula> parallel bits. It possesses the intrinsic advantages of current-mode signaling including high data rates, large signal swing, low switching noise injection, and superior signal integrity. The current-integrating receiver consisting of a transimpedance front-end, an integrator, and a sense amplifier with active inductor shunt peaking offers the key advantages of a low and tunable input impedance for channel termination, large bandwidth, and effective suppression of transient noise coupled to the channels. To assess the effectiveness of the proposed signaling scheme and the current-integrating receiver, a 4-bit parallel link consisting of four bipolar current-mode drivers, five 10-cm microstrip lines with FR4 substrate, and four proposed current-integrating receivers is implemented in UMC 0.13-<formula formulatype="inline"><tex>$\mu{\hbox {m}}$</tex></formula> 1.2-V CMOS technology and analyzed using <emphasis emphasistype="italic">SpectreRF</emphasis> from Cadence Design Systems with BSIM3.3V device models. Simulation results demonstrate that the proposed CMIS scheme and the current-integrating receiver are capable of transmitting parallel data at 2.5 GB/s. </para>