Abstract
The performance of many digital systems today is limited by the interconnection bandwidth between chips. Although the processing performance of a single chip has increased dramatically since the inception of the integrated circuit technology, the communication bandwidth between chips has not enjoyed as much benefit. Most CMOS chips, when communicating off-chip, drive unterminated lines with full-swing CMOS drivers. Such full-swing CMOS interconnect ring-up the line, and hence has a bandwidth that is limited by the length of the line rather than the performance of the semiconductor technology. Thus, as VLSI technology scales, the pin bandwidth does not improve with the technology, but rather remains limited by board and cable geometry, making off-chip bandwidth an even more critical bottleneck. In order to increase the I/O Bandwidth, some efficient high speed signaling standard must be used which considers the line termination, signal integrity, power dissipation, noise immunity etc In this work, a transmitter has been developed for high speed offchip communication. It consists of low speed input buffer, serializer which converts parallel input data into serial data and a current mode driver which converts the voltage mode input signals into current over the transmission line. Output of 32 low speed input buffers is fed to two serializer, each serializer converting 16 bit parallel data into serial data stream. Output of two serializers is fed to LVDS current mode driver. The serial link technique used in this work is the time division multiplex (TDM) and point-to-point technique. It means that the low-speed parallel signals are transferred to the high-speed serial signal at the transmitter end and the high-speed serial signal is transferred to the low-speed parallel signals at the receiver end. Serial link is the design of choice in any application where the cost of the communication channel is high and duplicating the links in large numbers is uneconomical.
Highlights
The ever-increasing processing speed of microprocessor motherboards, optical transmission links, chip-to-chip communications, etc., is pushing the off-chip data rate into the gigabits-per-second range
Off-chip high data rates were achieved by massive parallelism, with the disadvantages of increased complexity and cost for the IC package and the printed circuit board (PCB)
During one clock cycle each input parallel data is present in the serial output for equal amount of time. This can be be viewed as the low speed parallel data is getting converted to high speed serial data, the frequency of the data being increased by a factor of 16
Summary
The ever-increasing processing speed of microprocessor motherboards, optical transmission links, chip-to-chip communications, etc., is pushing the off-chip data rate into the gigabits-per-second range. Off-chip high data rates were achieved by massive parallelism, with the disadvantages of increased complexity and cost for the IC package and the printed circuit board (PCB). There are two methods for data transmission using transceivers - Single-Ended transmission and Differential transmission Both of them have their benefits & disadvantages. A single-ended system requires only one line per signal It is ideal when cabling and connector costs are more important than the signaling rate or transmission distance. Differential transmission addresses many of the shortcomings of single-ended solutions by using a pair of signal lines for each information channel. In addition to noise immunity, differential circuits radiate substantially less noise to the environment than single-ended circuits This is primarily due to the complementary current in each line of the signal pair canceling each other’s generated fields. Differential signaling adds cost and complexity in silicon and interconnecting hardware where it is roughly double that for a single-ended interface but signal integrity and signaling rate is much more superior as compared to single ended signaling
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