Current Field Programmable Gate Arrays Research Articles

Integrating Machine-Learning Probes in FPGA CAD: Why and How?

This article discusses the performance challenge that modern designs pose for current Field Programmable Gate Array (FPGA) design tools. It then explores how machine-learning probes can be used within the traditional FPGA design flow to improve performance. As proof of concept, the authors implement nine probes and integrate them into the placement step of the Verilog-to-Routing (VTR) tool. Each probe provides fast, accurate estimates of routing-resource utilization, which can be used to guide the placer towards more “routing-friendly” placement solutions or avoid futile routing attempts.

High-Level Synthesis Design of Scalable Ultrafast Ultrasound Beamformer With Single FPGA.

Ultrafast ultrasound imaging is essential for advanced ultrasound imaging techniques such as ultrasound localization microscopy (ULM) and functional ultrasound (fUS). Current ultrafast ultrasound imaging is challenged by the ultrahigh data bandwidth associated with the radio frequency (RF) signal, and by the latency of the computationally expensive beamforming process. As such, continuous ultrafast data acquisition and beamforming remain elusive with existing software beamformers based on CPUs or GPUs. To address these challenges, the proposed work introduces a novel method of implementing an ultrafast ultrasound beamformer specifically for ultrafast plane wave imaging (PWI) on a field programmable gate array (FPGA) by using high-level synthesis. A parallelized implementation of the beamformer on a single FPGA was proposed by 1) utilizing a delay compression technique to reduce the delay profile size, which enables both run-time pre-calculated delay profile loading from external memory and delay reuse, 2) vectorizing channel data fetching which is enabled by delay reuse, and 3) using fixed summing networks to reduce consumption of logic resources. Our proposed method presents two unique advantages over current FPGA beamformers: 1) high scalability that allows fast adaptation to different FPGA resources and beamforming speed demands by using Xilinx High-Level Synthesis as the development tool, and 2) allow a compact form factor design by using a single FPGA to complete the beamforming instead of multiple FPGAs. Current Xilinx FPGAs provide the capabilities of connecting up to 1024 ultrasound channels with a single FPGA and the newest JESD204B interface analog front end (AFE). This channel count is much more than the channel count needed by current linear arrays, which normally have 128 or 256 channels. With the proposed method, a sustainable average beamforming rate of 4.83 G samples/second in terms of input raw RF sample was achieved. The resulting image quality of the proposed beamformer was compared with the software beamformer on the Verasonics Vantage system for both phantom imaging and in vivo imaging of a mouse brain. Multiple imaging schemes including B-mode, power Doppler and ULM were assessed to verify that the image quality was not compromised for speed.

High Performance Computing PP-Distance Algorithms to Generate X-ray Spectra from 3D Models.

X-ray crystallography is a powerful method that has significantly contributed to our understanding of the biological function of proteins and other molecules. This method relies on the production of crystals that, however, are usually a bottleneck in the process. For some molecules, no crystallization has been achieved or insufficient crystals were obtained. Some other systems do not crystallize at all, such as nanoparticles which, because of their dimensions, cannot be treated by the usual crystallographic methods. To solve this, whole pair distribution function has been proposed to bridge the gap between Bragg and Debye scattering theories. To execute a fitting, the spectra of several different constructs, composed of millions of particles each, should be computed using a particle–pair or particle–particle (pp) distance algorithm. Using this computation as a test bench for current field-programmable gate array (FPGA) technology, we evaluate how the parallel computation capability of FPGAs can be exploited to reduce the computation time. We present two different solutions to the problem using two state-of-the-art FPGA technologies. In the first one, the main C program uses OmpSs (a high-level programming model developed at the Barcelona Supercomputing Center, that enables task offload to different high-performance computing devices) for task invocation, and kernels are built with OpenCL using reduced data sizes to save transmission time. The second approach uses task and data parallelism to operate on data locally and update data globally in a decoupled task. Benchmarks have been evaluated over an Intel D5005 Programmable Acceleration Card, computing a model of 2 million particles in 81.57 s – 24.5 billion atom pairs per second (bapps)– and over a ZU102 in 115.31 s. In our last test, over an up-to-date Alveo U200 board, the computation lasted for 34.68 s (57.67 bapps). In this study, we analyze the results in relation to the classic terms of speed-up and efficiency and give hints for future improvements focused on reducing the global job time.

Implementation of Aging Mechanism Analysis and Prediction for XILINX 7-Series FPGAs with a 28-nm Process.

Commercial off-the-shelf (COTS) field-programmable gate arrays (FPGAs) with a 28-nm process have become popular devices for computing systems. Although current generation FPGAs have advantages over previous models, the phenomenon of circuit aging has become more significant with the sharp reduction in the process size of FPGAs. Aging results in FPGA performance degradation over time and, ultimately, hard faults. However, few studies have focused on understanding aging mechanisms or estimating the aging trend of 28-nm FPGAs. For this, we used a ring oscillator (RO)-based test structure to extract data and build a dataset that could be used to predict aging trends and determine the primary aging mechanisms of 28-nm FPGAs. Moreover, we proposed a correction method to correct temperature-induced measurement errors in accelerated tests. Furthermore, we employed four machine learning (ML) technologies that were based on accurate measurement datasets to predict FPGA aging trends. In the experiment, 24 XILINX 7-series FPGAs (28 nm) were evaluated for 10+ years of circuit operation using accelerated tests. The results showed that the aging effects of negative-bias temperature instability (NBTI) was the primary aging mechanism. The correction method proposed in this paper could effectively eliminate measurement errors. In addition, the minimum prediction error rate of the ML model was only 0.292%.

Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non-arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.

A Dynamic Reconfigurable Architecture for Hybrid Spiking and Convolutional FPGA-Based Neural Network Designs

This work presents a dynamically reconfigurable architecture for Neural Network (NN) accelerators implemented in Field-Programmable Gate Array (FPGA) that can be applied in a variety of application scenarios. Although the concept of Dynamic Partial Reconfiguration (DPR) is increasingly used in NN accelerators, the throughput is usually lower than pure static designs. This work presents a dynamically reconfigurable energy-efficient accelerator architecture that does not sacrifice throughput performance. The proposed accelerator comprises reconfigurable processing engines and dynamically utilizes the device resources according to model parameters. Using the proposed architecture with DPR, different NN types and architectures can be realized on the same FPGA. Moreover, the proposed architecture maximizes throughput performance with design optimizations while considering the available resources on the hardware platform. We evaluate our design with different NN architectures for two different tasks. The first task is the image classification of two distinct datasets, and this requires switching between Convolutional Neural Network (CNN) architectures having different layer structures. The second task requires switching between NN architectures, namely a CNN architecture with high accuracy and throughput and a hybrid architecture that combines convolutional layers and an optimized Spiking Neural Network (SNN) architecture. We demonstrate throughput results from quickly reprogramming only a tiny part of the FPGA hardware using DPR. Experimental results show that the implemented designs achieve a 7× faster frame rate than current FPGA accelerators while being extremely flexible and using comparable resources.

Secure Computing Enclaves Using FPGAs

A new scheme for securing users' data and applications in public clouds and data centers using Field Programmable Gate Arrays (FPGAs) has been developed. This scheme incorporates all necessary protocols, hardware, and software components to provide protection against many known potential attacks including internal attacks. It achieves perfect forward secrecy, provides FPGA authentication and integrity checks, and securely establishes a symmetric session key between the user and the FPGA. A complete prototype has been implemented to show the feasibility of the proposed scheme with current FPGAs. Experimental results showed that an FPGA-based compute node can be set up in a cloud in 3.36s; 12.6 times faster than booting a medium-size conventional Virtual Machine (VM) on the same cloud. Based on the average global Internet speed, the time it takes to set up the FPGA-based machine from anywhere in the world was estimated to be 15s. Also, running an experimental secure image processing application on the FPGA took 50 percent less time than running the same application on a conventional state-of-the art processor (without a secure container).

FLASH: Fast, Parallel, and Accurate Simulator for HLS

A large semantic gap between a high-level synthesis (HLS) design and a low-level RTL simulation environment often creates a barrier for those who are not field-programmable gate array (FPGA) experts. Moreover, such a low-level simulation takes a long time to complete. Software HLS simulators can help bridge this gap and accelerate the simulation process; but their shortcoming is that they do not provide performance estimation. To make matters worse, we found that the current FPGA HLS commercial software simulators sometimes produce incorrect results. In order to solve these performance estimation and correctness problems while maintaining the high speed of software simulators, this article proposes a new HLS simulation flow named FLASH. The main idea behind the proposed flow is to extract scheduling information from the HLS tool and automatically construct an equivalent cycle-accurate simulation model while preserving C semantics. The experimental results show that FLASH runs three orders of magnitude faster than the RTL simulation.

UNILOGIC

One of the main characteristics of High-performance Computing (HPC) applications is that they become increasingly performance and power demanding, pushing HPC systems to their limits. Existing HPC systems have not yet reached exascale performance mainly due to power limitations. Extrapolating from today’s top HPC systems, about 100–200 MWatts would be required to sustain an exaflop-level of performance. A promising solution for tackling power limitations is the deployment of energy-efficient reconfigurable resources (in the form of Field-programmable Gate Arrays (FPGAs)) tightly integrated with conventional CPUs. However, current FPGA tools and programming environments are optimized for accelerating a single application or even task on a single FPGA device. In this work, we present UNILOGIC (Unified Logic), a novel HPC-tailored parallel architecture that efficiently incorporates FPGAs. UNILOGIC adopts the Partitioned Global Address Space (PGAS) model and extends it to include hardware accelerators, i.e., tasks implemented on the reconfigurable resources. The main advantages of UNILOGIC are that (i) the hardware accelerators can be accessed directly by any processor in the system, and (ii) the hardware accelerators can access any memory location in the system. In this way, the proposed architecture offers a unified environment where all the reconfigurable resources can be seamlessly used by any processor/operating system. The UNILOGIC architecture also provides hardware virtualization of the reconfigurable logic so that the hardware accelerators can be shared among multiple applications or tasks. The FPGA layer of the architecture is implemented by splitting its reconfigurable resources into (i) a static partition, which provides the PGAS-related communication infrastructure, and (ii) fixed-size and dynamically reconfigurable slots that can be programmed and accessed independently or combined together to support both fine and coarse grain reconfiguration. 1 Finally, the UNILOGIC architecture has been evaluated on a custom prototype that consists of two 1U chassis, each of which includes eight interconnected daughter boards, called Quad-FPGA Daughter Boards (QFDBs); each QFDB supports four tightly coupled Xilinx Zynq Ultrascale+ MPSoCs as well as 64 Gigabytes of DDR4 memory, and thus, the prototype features a total of 64 Zynq MPSoCs and 1 Terabyte of memory. We tuned and evaluated the UNILOGIC prototype using both low-level (baremetal) performance tests, as well as two popular real-world HPC applications, one compute-intensive and one data-intensive. Our evaluation shows that UNILOGIC offers impressive performance that ranges from being 2.5 to 400 times faster and 46 to 300 times more energy efficient compared to conventional parallel systems utilizing only high-end CPUs, while it also outperforms GPUs by a factor ranging from 3 to 6 times in terms of time to solution, and from 10 to 20 times in terms of energy to solution.

High-Capacity FPGA Router for Satellite Backbone Network

Satellite backbone networks provide a viable means of establishing broadband connectivity for remote, sparsely populated areas. In addition, satellite communication systems are well suited for airborne, maritime, and disaster relief environments. Technologies for links are continuing to improve in performance and power efficiency, making onboard regeneration and routing feasible within spacecraft power envelope. In this article, we implement and analyze a spaceborne router design integrated on a field-programmable gate array (FPGA). FPGA provides a flexibility needed to circumvent space radiation effects on chip circuitry, as they can be reconfigured at runtime. We explored scalability of the high-end state-of-the art FPGA chip family, and its ability to support high bit-rate satellite links: 10 Gbps satellite-to-ground links and 100 Gbps intersatellite links. Through implementation and testing, we confirm that the current FPGA technology can support space routers with very high data throughput.

Smart Sensor: SoC Architecture for the Industrial Internet of Things

Nowadays, the concept of intelligent manufacturing is being introduced, based on the integration of new advanced technologies, such as the Internet of Things (IoT), distributed control, data analysis, and cyber-security in the manufacturing area, with the aim of improving manufacturing processes and the articles produced. In this sense, new intelligent devices (Smart Sensors) should be developed that integrate several detection methods (sensors), real-time (RT) data analysis, and wired and/or wireless connectivity. The main contribution of this paper is the design, implementation, and experimental verification of an architecture of a Smart Sensor that satisfies the operational requirements needed by the Industrial IoT (IIoT). Considering the software and hardware adaptability that a Smart Sensor should have, this paper takes advantage of the characteristics of the current field programmable gate arrays (FPGAs) and SoC to implement a Smart Sensor for the IIoT. In this sense, the proposed Smart Sensor architecture incorporates RT operation features, the ability to perform local data analysis, high availability communication interfaces, such as high-availability seamless redundancy (HSR) and parallel redundancy protocol (PRP), interoperability (industrial protocols), and cyber-security. The architecture was implemented with hardware available in the market, IP cores, and Python libraries developed by third parties. Finally, to validate the applicability of the architecture in the industry, two test environments were implemented. In the first case, interoperability, high availability, synchronization, and local data processing are validated. The second case aims to determine the delay when adding encryption (cyber-security) in layer 2 communications.

Implementation of Processing Functions for Autonomous Power Quality Measurement Equipment: A Performance Evaluation of CPU and FPGA-Based Embedded System

Motivated by the effects of deregulation over power quality and the subsequent need of new types of measurements, this paper assesses different implementations of an estimate for the spectral kurtosis, considered as a low-level harmonic detection. Performance of a processor-based system is compared with a field programmable gate array (FPGA)-based solution, in order to evaluate the accuracy of this processing function for implementation in autonomous measurement equipment. The fourth-order spectrum, with applications in different fields, needs advanced digital signal processing, making it necessary to compare implementation alternatives. In order to obtain reproducible results, the implementations have been developed using common design and programming tools. Several characteristics of the implementations are compared, showing that the increasing complexity and reduced cost of the current FPGA models make the implementation of complex mathematical functions feasible. We show that FPGAs improve the processing capability of the best processor using an operating frequency 33 times lower. This fact strongly supports its implementation in hand-held instruments.

Towards LST split-window algorithm FPGA implementation for CubeSats on-board computations purposes

ABSTRACTNano, pico, and the so-called CubeSat satellites are taking place due to the emergent improvements in both high-performance nano and pico electronics and computational technologies. More than 1600 nanosats and CubeSats exist nowadays (i.e. 685 nanosats launched, 613 CubeSats launched, 405 nanosatellites in orbit, 321 operational nanosatellites, 71 nanosats destroyed on launch, etc.), with an incredible panoply of different constellations, governmental and non-governmental, high and easy to reach technologies, instruments in miniatures and missions from the military to universities and schools. This paper describes an approach to the implementation of the land surface temperature split-window (LST-SW) (Sobrino and Raissouni, IJRS 2000) algorithm structure based on the field programmable gate array (FPGA) technology. Due to the ever-increasing integrated circuit fabrication capabilities, the future of FPGA technology promises both higher densities and higher speeds for CubeSats on-board computations purposes. The research application shows the advantages of the used Xilinx Virtex-5 LX50 series FPGA approach in the LST-SW implementation with higher sampling rates than what is available from existing digital signal processing (DSP) chips, lower costs than an application specific integrated circuits (ASIC) for moderate volume applications and more flexibility than the alternate approaches. Since many current FPGA architectures are in-system programmable, the configuration of the device may be changed to implement different functionalities if required depending on the LST-SW parameters for each corresponding author. Finally, preliminary results show that the proposed LST-SW Xilinx Virtex-5 LX50 FPGA implementation approach is exceedingly flexible. Moreover, this implementation provides a considerable and promising performance that is suitable for future CubeSats on board LST-SW computations purposes.

Implementation of a high precision multi-measurement time-to-digital convertor on a Kintex-7 FPGA

Time-to-digital convertors (TDCs) based on field programmable gate array (FPGA) are becoming more and more popular. Multi-measurement is an effective method to improve TDC precision beyond the cell delay limitation. However, the implementation of TDC with multi-measurement on FPGAs manufactured with 28 nm and more advanced process is facing new challenges. Benefiting from the ones-counter encoding scheme, which was developed in our previous work, we implement a ring oscillator multi-measurement TDC on a Xilinx Kintex-7 FPGA. Using the two TDC channels to measure time-intervals in the range (0 ns–30 ns), the average RMS precision can be improved to 5.76 ps, meanwhile the logic resource usage remains the same with the one-measurement TDC, and the TDC dead time is only 22 ns. The investigation demonstrates that the multi-measurement methods are still available for current main-stream FPGAs. Furthermore, the new implementation in this paper could make the trade-off among the time precision, resource usage and TDC dead time better than ever before.

Parallel light configuration that increases the radiation tolerance of integrated circuits

Total ionizing dose tolerances of current integrated circuits are limited to 3–10 kGy because semiconductor devices are fundamentally vulnerable to radiation. However, using programmable architecture, the total ionizing dose tolerances of integrated circuits can be increased if the integrated circuits can be repaired each time a permanent failure occurs. Nevertheless, current programmable devices cannot allow such repairable use because their serial programming functions fail immediately, even if only a few transistors on the devices are damaged. To increase the radiation tolerance of integrated circuits, this paper presents a proposal of a new optoelectronic programmable device with a parallel light configuration architecture instead of current field programmable gate arrays which have a serial configuration architecture. This demonstration confirms 1.9 MGy radiation tolerance on an optoelectronic programmable device using a non-radiation-hardened standard complementary metal oxide semiconductor process.

ProNoC: A low latency network-on-chip based many-core system-on-chip prototyping platform

Network-on-chip (NoC) is an emerging interconnect infrastructure to address the scalability limitation of conventional shared bus architecture for many-core system-on-chip (MCSoC). Current field-programmable gate arrays (FPGAs) have over million lookup tables, making it possible to prototype a complete NoC-based MCSoC on a single FPGA device. FPGA prototyping allows rapid system verification and optimum design parameters estimation. However, existing NoC-based MCSoC prototypes are usually adopting simple NoC architectural functionality. These NoC prototypes cannot represent a realistic projection of the state-of-the-art application-specific integrated circuit (ASIC) NoCs as these prototypes have limited overall system performance. This paper presents ProNoC, an integrated tool for rapid prototyping and validation of NoC-based MCSoC projects targeting FPGA devices. ProNoC adopts most advanced NoC features such as the support of virtual channel (VC), virtual network, low latency routing and different routing algorithms. Results show that NoC interconnect in ProNoC outperforms CONNECT, the most recent VC based prototype NoC with lower logic cell utilization, higher maximum operating frequency, higher average saturation throughput, and lower average communication latency. Moreover, ProNoC is equipped with graphical user interface to facilitate the development of MCSoC prototypes on FPGA platforms.

High-speed scrubbing demonstration using an optically reconfigurable gate array.

This paper presents a proposal for a high-speed scrubbing method based on an optically reconfigurable gate array (ORGA) architecture. A salient concern for current field programmable gate arrays (FPGAs) used in high-radiation environments is the high frequency of soft-errors occurring on their configuration memories. Even if triple modular redundancy is used for implementations on FPGAs, soft-error tolerance issues on the configuration memories cannot be alleviated. This paper therefore presents a high-speed scrubbing method that is applicable to ORGA architectures, in addition to its experimental demonstration on an ORGA-VLSI. The mean time between soft-errors (MTBF) on the ORGA configuration memory has been analyzed theoretically: the MTBF can be extended to 1.35-1.89 million times longer than those of current FPGAs.

Array Multipliers for High Throughput in Xilinx FPGAs with 6-Input LUTs

Multiplication is the dominant operation for many applications implemented on field-programmable gate arrays (FPGAs). Although most current FPGA families have embedded hard multipliers, soft multipliers using lookup tables (LUTs) in the logic fabric remain important. This paper presents a novel two-operand addition circuit (patent pending) that combines radix-4 partial-product generation with addition and shows how it can be used to implement two’s-complement array multipliers. The circuit is specific to modern Xilinx FPGAs that are based on a 6-input LUT architecture. Proposed pipelined multipliers use 42%–52% fewer LUTs, and some versions can be clocked up to 23% faster than delay-optimized LogiCORE IP multipliers. This allows 1.72–2.10-times as many multipliers to be implemented in the same logic fabric and potentially offers 1.86–2.58-times the throughput by increasing the clock frequency.

FPGA TECHNOLOGY IN PROCESS TOMOGRAPHY

The aims of this paper are to provide a review of the process tomography applications employing field programmable gate arrays (FPGA) and to understand current FPGA related researches, in order to seek for the possibility to applied FPGA technology in an ultrasonic process tomography system. FPGA allows users to implement complete systems on a programmable chip, meanwhile, five main benefits of applying the FPGA technology are performance, time to market, cost, reliability, and long-term maintenance. These advantages definitely could help in the revolution of process tomography, especially for ultrasonic process tomography and electrical process tomography. Future work is focused on the ultrasonic process tomography for chemical process column investigation using FPGA for the aspects of low cost, high speed and reconstructed image quality.

Fast Power and Performance Evaluation of FPGA-Based Wireless Communication Systems

In this paper, a new and efficient methodology is proposed to quickly and precisely evaluate the power consumption and performance of wireless communication base-band systems implemented in field-programmable gate arrays (FPGAs). As the complexity of such systems is still growing, being able to estimate both power and performance of a design has become a major issue. FPGA devices constitute a promising technology in this highly constrained context. However, to respect their power budget, designers need to explore the design space very soon in the design process. This is performed prior to any implementation. Based on the innovative definition of a scenario, which enables comparison among wireless communication applications in a formal manner, each parameter can be evaluated to meet the power-performance tradeoff. In this paper, the proposed methodology is realized in two steps using a low-level characterization process and high-level system modeling. Another major contribution consists in considering components’ time activity to refine power estimations results. We demonstrate the effectiveness of the proposed methodology throughout several domain-specific use cases, with a focus on hardware base-band processing in the wireless communication domain. As compared with current low-level FPGAs vendor tools, an important speedup factor is obtained, and a maximal relative error lower than 5% is reached.