Current Field Programmable Gate Arrays Research Articles

Radiation-hardened optically reconfigurable gate array exploiting holographic memory characteristics

In this paper, we present a proposal for a radiation-hardened optically reconfigurable gate array (ORGA). The ORGA is a type of field programmable gate array (FPGA). The ORGA configuration can be executed by the exploitation of holographic memory characteristics even if 20% of the configuration data are damaged. Moreover, the optoelectronic technology enables the high-speed reconfiguration of the programmable gate array. Such a high-speed reconfiguration can increase the radiation tolerance of its programmable gate array to 9.3 × 104 times higher than that of current FPGAs. Through experimentation, this study clarified the configuration dependability using the impulse-noise emulation and high-speed configuration capabilities of the ORGA with corrupt configuration contexts. Moreover, the radiation tolerance of the programmable gate array was confirmed theoretically through probabilistic calculation.

Timing-Driven Titan

Benchmarks play a key role in Field-Programmable Gate Array (FPGA) architecture and CAD research, enabling the quantitative comparison of tools and architectures. It is important that these benchmarks reflect modern large-scale systems that make use of heterogeneous resources; however, most current FPGA benchmarks are both small and simple. In this artile, we present Titan, a hybrid CAD flow that addresses these issues. The flow uses Altera’s Quartus II FPGA CAD software to perform HDL synthesis and a conversion tool to translate the result into the academic Berkeley Logic Interchange Format (BLIF). Using this flow, we created the Titan23 benchmark set, which consists of 23 large (90K--1.8M block) benchmark circuits covering a wide range of application domains. Using the Titan23 benchmarks and an enhanced model of Altera’s Stratix IV architecture, including a detailed timing model, we compare the performance and quality of VPR and Quartus II targeting the same architecture. We found that VPR is at least 2.8 × slower, uses 6.2 × more memory, 2.2 × more wire, and produces critical paths 1.5 × slower compared to Quartus II. Finally, we identified that VPR’s focus on achieving a dense packing and an inability to take apart clusters is responsible for a large portion of the wire length and critical path delay gap.

FPGA Based Packet Classification Using Multi-Pipeline Architecture

This paper proposes a decision-tree-based linear multi-pipeline architecture on FPGA’s for packet sorting. We reflect on the next-generation packet classification problems where more than 5-tuple packet header fields has been classified. From traditional fixed 5-tuple matching, Multi-field packet classification has been evolved for flexible matching with arbitrary combination of numerous packet header fields. The recently proposed Open Flow switching requires classifying each packet using up to 12-tuple packet header fields. It become a great task to develop scalable solutions for next-generation packet classification that support larger rule sets, additional packet header fields and higher throughput. This paper proposes a 2-D multi-pipeline decision-tree-based architecture for next-generation packet classification which exploits the abundant parallelism and other desirable features such as current field-programmable gate arrays (FPGAs),. We propose several optimization techniques for the state-of-the-art decision-tree-based algorithm by examine the various traditional 5-tuple packet classification methods. By using set of 12-tuple rules, the framework has been developed to partition the rule set into multiple subsets each of which is built into an optimized decision tree. To maximize the memory utilization. a tree-to-pipeline mapping scheme is carefully designed while underneath high throughput. Our proposed architecture can store up to 1K synthetic 12-tuple rules or 10K real-life 5-tuple rules in on-chip memory of a single up to date FPGA, and maintain 80 or 40 Gbps throughput for least packets of size (40 bytes) respectively. To utilize the memory properly and to sustaining high throughput, a mapping scheme based on tree-to-pipeline is designed carefully. This paper deal with the profuse parallelism and other preferred features provided by present field-programmable gate arrays and propose a 2-D multi-pipeline decision tree based architecture for next-generation packet sorting. The Verilog Hardware description languages (VHDL) are used to design the proposed architecture and synthesized using Xilinx Software.

Secure distribution infrastructure for hardware digital contents

Field-programmable gate array (FPGA) reconfigurability creates the possibility of distributing hardware cores pretty much like software digital contents, possibly on payment or on a subscription basis. In this work, the authors propose an infrastructure for the secure distribution of such hardware digital contents (HDCs). Aimed at the practical realisation of the envisioned scenario, this study analyses the security-related features of the current FPGA devices, for example, (partial) bitstream encryption, and takes them as the underlying constraints for the definition of the infrastructure. This work clearly identifies the roles involved in the secure distribution process, including a trusted third-party entity, and introduces a cryptographic protocol ensuring the confidentiality and the trustworthiness of partial bitstreams dynamically downloaded to the user's device. This study also presents a detailed case-study application scenario, namely the secure distribution of image codec components, providing a few quantitative results and demonstrating the limited overhead incurred by the proposed solution in terms of time and area costs. The conclusive section of this study discusses the lesson learned from this work and draws a few proposals for the evolution of security-related FPGA features which may enable the full realisation of the secure HDC distribution concept.

A parametric-based performance evaluation and design trade-offs for interconnect architectures using FPGAs for networks-on-chip

Network-on-Chip (NoC) interconnect fabrics are categorized according to trade-offs among latency, throughput, speed, and silicon area, and the correctness and performance of these fabrics in Field-Programmable Gate Array (FPGA) applications are assessed through experimentation and simulation. In this paper, we propose a consistent parametric method for evaluating the FPGA performance of three common on-chip interconnect architectures namely, the Mesh, Torus and Fat-tree architectures. We also investigate how NoC architectures are affected by interconnect and routing parameters, and demonstrate their flexibility and performance through FPGA synthesis and testing of 392 different NoC configurations. In this process, we found that the Flit Data Width (FDW) and Flit Buffer Depth (FBD) parameters have the heaviest impact on FPGA resources, and that these parameters, along with the number of Virtual Channels (VCs), significantly affect reassembly buffering and routing and logic requirements at NoC endpoints. Applying our evaluation technique to a detailed and flexible cycle accurate simulation, we drive the three NoC architectures using benign (Nearest Neighbor and Uniform) and adversarial (Tornado and Random Permutation) traffic patterns with different numbers of VCs, producing a set of load–delay curves. The results show that by strategically tuning the router and interconnect parameters, the Fat-tree network produces the best utilization of FPGA resources in terms of silicon area, clock frequency, critical path delays, network cost, saturation throughput, and latency, whereas the Mesh and Torus networks showed comparatively high resource costs and poor performance under adversarial traffic patterns. From our findings it is clear that the Fat-tree network proved to be more efficient in terms of FPGA resource utilization and is compliant with the current Xilinx FPGA devices. This approach will assist engineers and architects in establishing an early decision in the choice of right interconnects and router parameters for large and complex NoCs. We demonstrate that our approach substantially improves performance under a large variety of experimentation and simulation which confirm its suitability for real systems.

An Analytical Model for Evaluating Static Power of Homogeneous FPGA Architectures

As capacity of the field-programmable gate arrays (FPGAs) continues to increase, power dissipated in the logic and routing resources has become a critical concern for FPGA architects. Recent studies have shown that static power is fast approaching the dynamic power in submicron devices. In this article, we propose an analytical model for relating homogeneous island-style-based FPGA architecture to static power. Current FPGA power models are tightly coupled with CAD tools. Our CAD-independent model captures the static power for a given FPGA architecture based on estimates of routing and logic resource utilizations from a pre-technology mapped netlist. We observe an average correlation ratio (C-Ratio) of 95% and a minimum absolute percentage error (MAPE) rate of 15% with respect to the experimental results generated by the Versatile Placement Routing (VPR) tool over the MCNC benchmarks. Our model offers application engineers and FPGA architects the capability to evaluate the impact of their design choices on static power without having to go through CAD-intensive investigations.

“Our Original 3D Idea Still Has To Happen; And It Will”

Ivo Bolsens is senior vice president (SVP) and chief technology officer (CTO) at Xilinx, a leading supplier of field-programmable gate arrays (FPGAs). At Xilinx, he is responsible for advanced technology development, as well as the company's research laboratories and university program. Design & Test's Erik Jan Marinissen met with Dr. Bolsens in November 2012 during the IEEE International Test Conference in Anaheim, CA,USA, where Bolsens was the opening keynote speaker at the co-located 3D-TEST Workshop . Shortly prior to his keynote talk, this interview took place during lunch at a Disneyland restaurant, covering Bolsens' career from IMEC to Xilinx, current and future FPGAs, the differences between research and company environments, and Xilinx recent 3D-FPGA product.

Scalable Packet Classification on FPGA

Multi-field packet classification has evolved from traditional fixed 5-tuple matching to flexible matching with arbitrary combination of numerous packet header fields. For example, the recently proposed OpenFlow switching requires classifying each packet using up to 12-tuple packet header fields. It has become a great challenge to develop scalable solutions for next-generation packet classification that support higher throughput, larger rule sets and more packet header fields. This paper exploits the abundant parallelism and other desirable features provided by current field-programmable gate arrays (FPGAs), and proposes a decision-tree-based, 2-D multi-pipeline architecture for next-generation packet classification. We revisit the techniques for traditional 5-tuple packet classification and propose several optimization techniques for the state-of-the-art decision-tree-based algorithm. Given a set of 12-tuple rules, we develop a framework to partition the rule set into multiple subsets each of which is built into an optimized decision tree. A tree-to-pipeline mapping scheme is carefully designed to maximize the memory utilization while sustaining high throughput. The implementation results show that our architecture can store either 10K real-life 5-tuple rules or 1K synthetic 12-tuple rules in on-chip memory of a single state-of-the-art FPGA, and sustain 80 and 40 Gbps throughput for minimum size (40 bytes) packets, respectively.

An analytical model for multilevel performance prediction of Multi-FPGA systems

Power limitations in semiconductors have made explicitly parallel device architectures such as Field-Programmable Gate Arrays (FPGAs) increasingly attractive for use in scalable systems. However, mitigating the significant cost of FPGA development requires efficient design-space exploration to plan and evaluate a range of potential algorithm and platform choices prior to implementation. The authors propose the RC Amenability Test for Scalable Systems (RATSS), an analytical model which enables straightforward, fast, and reasonably accurate performance prediction prior to implementation by extending current modeling concepts to multi-FPGA designs. RATSS provides a comprehensive strategic model to evaluate applications based on the computation and communication requirements of the algorithm and capabilities of the FPGA platform. The RATSS model targets data-parallel applications on current scalable FPGA systems. Three case studies with RATSS demonstrate nearly 90% prediction accuracy as compared to corresponding implementations.

Field-programmable gate array implementation of a probabilistic neural network for motor cortical decoding in rats

A practical brain–machine interface (BMI) requires real-time decoding algorithms to be realised in a portable device rather than a personal computer. In this article, a field-programmable gate array (FPGA) implementation of a probabilistic neural network (PNN) is proposed and developed to decode motor cortical ensemble recordings in rats performing a lever-pressing task for water rewards. A chronic 16-channel microelectrode array was implanted into the primary motor cortex of the rat to record neural activity, and the pressure signal of the lever were recorded simultaneously. To decode the pressure value from neural activity, both Matlab-based and FPGA-based mapping algorithms using a PNN were implemented and evaluated. In the FPGA architecture, training data of the network were stored in random access memory (RAM) blocks and multiply–add operations were realised by on-chip DSP48E slices. In the approximation of the activation function, a Taylor series and a look-up table (LUT) are used to achieve an accurate approximation. The results of FPGA implementation are as accurate as the realisation of Matlab, but the running speed is 37.9 times faster. This novel and feasible method indicates that the performance of current FPGAs is competent for portable BMI applications.

Low-Power Programmable FPGA Routing Circuitry

We consider circuit techniques for reducing field-programmable gate-array (FPGA) power consumption and propose a family of new FPGA routing switch designs that are programmable to operate in three different modes: high-speed, low-power, or sleep. High-speed mode provides similar power and performance to traditional FPGA routing switches. In low-power mode, speed is curtailed in order to reduce power consumption. Leakage is reduced by 28%-52% in low-power versus high-speed mode, depending on the particular switch design selected. Dynamic power is reduced by 28%-31% in low-power mode. Leakage power in sleep mode, which is suitable for unused routing switches, is 61%-79% lower than in high-speed mode. Each of the proposed switch designs has a different power/area/speed tradeoff. All of the designs require only minor changes to a traditional routing switch and involve relatively small area overhead, making them easy to incorporate into current commercial FPGAs. The applicability of the new switches is motivated through an analysis of timing slack in industrial FPGA designs. It is observed that a considerable fraction of routing switches may be slowed down (operate in low-power mode), without impacting overall design performance.

Design and Demonstration of a Fully Integrated Multi-Technology FPGA: A Reconfigurable Architecture for Photonic and Other Multi-Technology Applications

Field-programmable gate arrays (FPGAs) have revolutionized programmable/reconfigurable digital logic technology. However, one limitation of current FPGAs is that the user is limited to strictly electronic designs. Thus, they are not suitable for applications that are not purely electronic, such as optical communications, photonic information processing systems and other multi-technology applications. While a wide variety of multi-technology devices ranging from microelectromagnetic systems (MEMS) devices, analog devices, photonic information processing devices, telecommunication and digital data processing systems to biological and chemical sensors have been implemented, research in this area has for the most part been limited to systems built with application-specific devices. While these designs are well optimized for a specific application, they do not provide the flexibility associated with reconfigurable/programmable hardware. As with any application-specific integrated circuit (ASIC), this approach is very costly, and the turnaround time between design iterations may be several months. The difficulty of using custom designed multi-technology VLSI components is overcome in the present research with the introduction of a multi-technology FPGA (MT-FPGA) with innovative system architecture. The proposed new class of field programmable device will extend the flexibility, rapid prototyping and reusability benefits associated with conventional FPGA technology into photonic and other multi-technology domain and give rise to the development of a wider class of programmable and embedded integrated systems.

Power and Area Optimization for Run-Time Reconfiguration System On Programmable Chip Based on Magnetic Random Access Memory

In recent years, magnetic random access memory (MRAM) based run-time system on programmable chip (SOPC) has been proposed as a solution to the critical drawbacks of current field programmable gate arrays (FPGAs), such as long (re)boot latency, high standby power, and limits for run time reconfiguration. However, the integration of MRAM in FPGA circuits brings its own problems, including large die area and high dynamic power for the switching circuit. In this paper, we present some solutions to overcome the power and area constraints and thereby improve the performance of MRAM based SOPC. We have done simulations and calculations based on the STMicroelectronics 90 nm design kit and a complete magnetic tunnel junction model.

Programmable optically reconfigurable gate array architecture and its writer

Recently, optically reconfigurable gate arrays (ORGAs), which consist of a gate array VLSI, a holographic memory, and a laser array, have been developed to achieve huge virtual gate counts that vastly surpass those of currently available VLSIs. By exploiting the large storage capacity of a holographic memory, VLSIs with more than 1 teragate counts will be producible. However, compared with current field programmable gate arrays, conventional ORGAs have one important shortcoming: they cannot be reprogrammed after fabrication. To reprogram ORGAs, a holographic memory must be disassembled from its ORGA package, then reprogrammed outside of the ORGA package using a holographic memory writer. It must then be implemented onto the ORGA package with high precision techniques beyond that which can be provided by manual assembly. Therefore, to improve this shortcoming, this paper proposes what is believed to be the world's first programmable ORGA architecture with no disassembly. Finally, the availability of this architecture is discussed based on the experimental results.

Built-in-Self-Test of FPGAs With Provable Diagnosabilities and High Diagnostic Coverage With Application to Online Testing

We present novel and efficient methods for built-in self-test (BIST) of field-programmable gate arrays (FPGAs) for detection and diagnosis of permanent faults in current, as well as emerging, technologies that are expected to have high fault densities. Our basic BIST methods can be used in both online and offline testing scenarios, although we focus on the former in this paper. We present 1- and 2-diagnosable BISTer designs that make up a ROving TEster (ROTE). Due to their provable diagnosabilities, these BISTers can avoid time-intensive adaptive diagnosis without significantly compromising diagnostic coverage-the percentage of faults correctly diagnosed. We also develop functional testing methods that test programmable logic blocks (PLBs) in only two circuit functions that will be mapped to them as the ROTE moves across a functioning FPGA. We extend our basic BISTer designs to those with test-pattern generators (TPGs) using multiple PLBs to more efficiently test the complex PLBs of current commercial FPGAs and to also prove the diagnosabilities of these designs. Simulation results show that our 1-diagnosable functional-test-based BISTer with a three-PLB TPG has very high diagnostic coverages-for example, for a random-fault distribution, our nonadaptive-diagnosis methods provide diagnostic coverages of 96% and 88% at fault densities of 10% and 25%, respectively, whereas the previous best nonadaptive-diagnosis method of the STAR-3 t 2 BISTer has diagnostic coverages of about 75% and 55% at these fault densities.

A Low-Power Reconfigurable Logic Array Based on Double-Gate Transistors

A fine-grained reconfigurable architecture based on double gate technology is proposed and analyzed. The logic function operating on the first gate of a double-gate (DG) transistor is reconfigured by altering the charge on its second gate. Each cell in the array can act as logic or interconnect, or both, contrasting with current field-programmable gate array structures in which logic and interconnect are built and configured separately. Simulation results are presented for a fully depleted SOI DG-MOSFET implementation and contrasted with two other proposals from the literature based on directed self-assembly.

Routability of Network Topologies in FPGAs

A fundamental difference between application-specific integrated circuits (ASICs) and field-programmable gate arrays (FPGAs) is that the wires in ASICs are designed to match the requirements of a particular design. Conversely, in an FPGA, the area is fixed and the routing resources exist whether or not they are used. In this paper, we investigate how well several common network topologies map onto a modern FPGA routing fabric. Different multiprocessor network topologies with between 8 and 64 nodes are mapped to a single large FPGA. Except for the fully-connected networks, it is observed that the difference in logic resources used and routing overhead among these topologies is insignificant for the systems tested. Fully-connected networks up to about 22 nodes are also feasible on the same FPGA although the logic and routing utilization clearly grows much faster. The conclusion is that a modern FPGA fabric is very rich in resources and capable of supporting highly interconnected topologies. For systems with a modest number of nodes implemented on current large FPGAs, it is not necessary to use the connectivity-limited topologies typically used for networks-on-chip. Rather, direct point-to-point connections between all communicating nodes can be considered.

Real-time face detection and lip feature extraction using field-programmable gate arrays

This paper proposes a new technique for face detection and lip feature extraction. A real-time field-programmable gate array (FPGA) implementation of the two proposed techniques is also presented. Face detection is based on a naive Bayes classifier that classifies an edge-extracted representation of an image. Using edge representation significantly reduces the model's size to only 5184 B, which is 2417 times smaller than a comparable statistical modeling technique, while achieving an 86.6% correct detection rate under various lighting conditions. Lip feature extraction uses the contrast around the lip contour to extract the height and width of the mouth, metrics that are useful for speech filtering. The proposed FPGA system occupies only 15050 logic cells, or about six times less than a current comparable FPGA face detection system.

A system approach for partially reconfigurable architectures

The increasing logic density of current Field Programmable Gate Arrays (FPGA) enables the integration of whole systems on one programmable chip. Using concepts of partial dynamic reconfiguration allows the adaptation of complex systems to changing requirements at run-time. In this paper we present a realisable approach for dynamic system integration on Xilinx Virtex FPGAs. In contrast to existing approaches that consider fixed slots for module placement, our approach allows fine-grained placement of modules with variable width along a horizontal communication infrastructure. By simulation we show that the proposed 1D-approach outperforms 2D-approaches by means of the device utilisation and external fragmentation.

Real-time image processing with a compact FPGA-based systolic architecture

In this paper, a configurable systolic architecture on a chip for real-time window-based image processing is presented. The architecture was specially designed to implement efficiently, both in performance and hardware resource utilization, window-based image operators under real-time constraints. The computational core of the architecture is a configurable 2D systolic array of processing elements, which can provide throughputs over tenths of Giga Operations per Second (GOPs). The architecture employs a novel-addressing scheme that significantly reduces the memory access overhead and makes explicit the data parallelism at a low temporal storage cost. A specialized processing element, called Configurable Window Processor (CWP), was designed to cover a broad range of window-based image algorithms. The functionality of the CWPs can be modified through configuration registers according to a given application. For a current Field Programmable Gate Array (FPGA) prototype of a 7×7 systolic array, the architecture provides a throughput of 3.16 GOPs at a 60 MHz clock frequency. The processing time for a 7×7 generic window-based image operator on 512×512 gray-level images is 8.35 ms. The implemented window-based image operators include generic image convolution, gray-level image morphology and template matching. According to theoretical and experimental results, the architecture compares favorably with other dedicated architectures in terms of performance and hardware resource utilization.