Mapping Arbitrary Logic Functions onto Carry Chains in FPGAs

Raouf Senhadji-Navarro,Ignacio Garcia-Vargas

doi:10.3390/electronics11010027

Raouf Senhadji-Navarro, Ignacio Garcia-Vargas

Open Access

https://doi.org/10.3390/electronics11010027

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Journal: Electronics	Publication Date: Dec 22, 2021
Citations: 7	License type: CC BY 4.0

Affiliation: Universidad de Sevilla

Abstract

Current Field Programmable Gate Arrays (FPGAs) provide fast routing links and special logic to perform carry operations; however, these resources can also be used to implement non-arithmetic circuits. In this paper, a new approach for mapping logic functions onto carry chains is presented. Unlike other approaches, the proposed technique can be applied to any logic function. The presented technique includes: (1) an architecture that is composed of blocks that implement AND and OR functions (called CANDs and CORs, respectively) by means of Look-Up-Tables (LUTs) and carry-chain resources; and (2) a mapping algorithm to reduce both the delay of the critical path and the number of used FPGA resources. The algorithm uses a heuristic to interconnect CORs and CANDs in order to reduce the delay. The problem of mapping the maxterms (or minterms) of a function to LUTs has been modelled as a Set Bin Packing (SBP) problem. Since SBP is NP-Hard, a greedy algorithm has been proposed, which is based on the First Fit Decreasing (FFD) heuristic. The results obtained have been compared with the conventional technique using both speed and area optimization. For this purpose, a large synthetic set of test cases has been generated. The proposed technique improves both the speed and area results for the vast majority of functions whose conventional implementation requires more than four logic levels. It is important to highlight that the improvement of one parameter (speed or area) is not achieved at the expense of the other.

Highlights

Field Programmable Gate Arrays (FPGAs) have established themselves as one of the preferred digital implementation platforms in a plethora of current industrial applications [1]
Following the principle called “use it or lose it”, different works in the literature have proposed an unconventional use of FPGA resources; a typical example is the use of embedded memory blocks to implement finite state machines [4,5,6,7,8,9,10]
Optimizing the critical path of a circuit is essential to achieving a high performance; in many cases, this is accomplished by including special resources in FPGAs

Summary

Introduction

Field Programmable Gate Arrays (FPGAs) have established themselves as one of the preferred digital implementation platforms in a plethora of current industrial applications [1]. FPGAs have evolved from a simple device for integrating glue-logic to the current complex devices, which includes more than 5 million logic cells with a host of other features such as embedded processors, DSP blocks or embedded memory blocks [2,3] These characteristics make these devices ideal as reconfigurable computing platforms for real applications, allowing the mapping of complex algorithms onto hardware to achieve the demanding performance of current applications. In circuits such as parity generators or comparators, the chain communicates the cumulative information needed to perform these computations [11] For this reason, current FPGAs provide fast routing links and special logic to perform carry operations.

Related Works

Background

Implementation of Arbitrary Logic Functions Using Carry Chains

Experimental Results

Conclusions and Future Work