Current-feedback Instrumentation Amplifier Research Articles

Biopotential multi-path current feedback instrumentation amplifier with automatic offset cancellation loop for resistive bridge microsensors

<span lang="EN-US">This study introduces a refined current feedback instrumentation amplifier (CFIA) specifically designed for amplifying biopotential signals that originate from resistive-bridge sensors. The proposed architecture uniquely incorporates a multipath chopper-stabilized CFIA which has been developed to minimize the effects of bridge offsets, while maintaining low power usage, high input impedance, and reduced noise characteristics. The engineering blueprint employs a ripple reduction loop (RRL) to mitigate output ripple caused by chopper up-modulation. To speed up offset cancellation and to limit the offset caused by bridge mismatch, an automatic offset cancellation loop (AOCL) circuit is integrated within the analog front end (AFE). Crafted using a conventional 0.18 µm CMOS process, the CFIA in this design provides adjustable gain between 20.35 dB to 55.14 dB, with a power supply rejection ratio (PSRR) and a common mode rejection ratio (CMRR) of 103 dB and 114 dB, respectively. The system demonstrates an input-referred noise (IRN) value of 16 ηV/√Hz at 200 Hz frequency, equivalent to a noise efficiency factor (NEF) of 5.18. Operating from a supply voltage of 1.8V, the AFE shows a power consumption of 291 μW.</span>

Low-Cost Indirect Measurements for Power-Efficient In-Field Optimization of Configurable Analog Front-Ends with Self-X Properties: A Hardware Implementation

This paper presents a practical implementation and measurement results of power-efficient chip performance optimization, utilizing low-cost indirect measurement methods to support self-X properties (self-calibration, self-healing, self-optimization, etc.) for in-field optimization of analog front-end sensory electronics with XFAB 0.35 µm complementary metal oxide semiconductor (CMOS) technology. The reconfigurable, fully differential indirect current-feedback instrumentation amplifier (CFIA) performance is intrinsically optimized by employing a single test sinusoidal signal stimulus and measuring the total harmonic distortion (THD) at the output. To enhance the optimization process, the experience replay particle swarm optimization (ERPSO) algorithm is utilized as an artificial intelligence (AI) agent, implemented at the hardware level, to optimize the performance characteristics of the CFIA. The ERPSO algorithm extends the selection producer capabilities of the classical PSO methodology by incorporating an experience replay buffer to mitigate the likelihood of being trapped in local optima. Furthermore, the CFIA circuit has been integrated with a simple power-monitoring module to assess the power consumption of the optimization solution, to achieve a power-efficient and reliable configuration. The optimized chip performance showed an approximate 34% increase in power efficiency while achieving a targeted THD value of −72 dB, utilizing a 1 Vp-p differential input signal with a frequency of 1 MHz, and consuming approximately 53 mW of power. Preliminary tests conducted on the fabricated chip, using the default configuration pattern extrapolated from post-layout simulations, revealed an unacceptable performance behavior of the CFIA. Nevertheless, the proposed in-field optimization successfully restored the circuit’s performance, resulting in a robust design that meets the performance achieved in the design phase.

Novel tunable current feedback instrumentation amplifier based on BBFC OP-AMP for biomedical applications with low power and high CMRR

The paper presents a novel low power, low noise and high CMRR current feedback instrumentation amplifier (CFIA) design for biomedical signal acquisition i.e. EEG/ECG applications is presented. The proposed instrumentation amplifier performance is evaluated using 0.18μm, CMOS technology with 1.8 V supply and results are obtained in Cadence EDA tool. The proposed CFIA is implemented using a dual output bandwidth boosted folded cascode operational amplifier (BBFC OP-AMP) active block. In this paper the proposed CFIA performance parameters has been considered for optimization to get better results by using the idea of signal to noise ratio (SNR) with Taguchi design of experiments (Taguchi DoE) and analysis of variance (ANOVA) to estimate the most important independent variable which control the performance of the design. The bias voltage, channel length and width of input MOS transistors have been selected to optimize the proposed circuit performance. The proposed CFIA structure have 50.33 to 69.67 dB tunable differential gain, common mode rejection ratio (CMRR) of 143.19 dB, tunable bandwidth of 148.24 kHz to 1.31 MHz, dynamic range (DR) of 74.31 dB and 297.73 dB of figure of merit (FoM). The CFIA shows an equivalent input referred noise (IRN) of 0.586 μV at 0.1 Hz to 148.24 kHz frequency range, with total power dissipation of 102.73 μW and occupies 8194μm2 of core area. The simulation results of the proposed CFIA are close to the predicted solution obtained from ANOVA. The PVT analysis and post layout simulation has been performed to check the robustness of the proposed design. The proposed design has been compared with the other existing literature which shows the competence of the design.

0.02 °/h, 0.004°/√h, 6.3-mA NEMS Gyroscope With Integrated Circuit

This work introduces a system formed by an integrated circuit and a micro-machined piezoresistive gyroscope, with navigation grade performance. After discussing the specifications in terms of maximum allowed electronic noise, so not to worsen the thermo-mechanical noise limits, three different front-end topologies are analysed, and the current-feedback instrumentation amplifier is chosen as the optimal solution in terms of noise and current consumption. After coupling to a gyroscope based on nano-gauges, the system demonstrates 200 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">dps</i> full-scale, 0.02 °/h stability and 0.004 °/ √ h angle random walk, confirming navigation-grade performance at a current consumption well below 10 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mA</i> and an overall power consumption below 40 <italic xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">mW</i> .

Low-Noise, Low-Power Readout IC for Two-Electrode ECG Recording Using Common-Mode Charge Pump for Robust 20-VPP Common-Mode Interference

A low-noise and -power readout integrated circuit (IC) for two-electrode electrocardiogram (ECG) recording is developed in this study using a common-mode charge pump (CMCP) for a robust 20-VPP common-mode interference (CMI). Two-electrode ECG recording offers more comfort than three-electrode ECG recording. Contrasting to the three-electrode ECG recording, the two-electrode ECG recording is affected by CMI during measurements; the intervention of a large CMI will distort the ECG signal measurement. To achieve robustness for the CMI, the proposed ECG readout IC adopts CMCP—it uses switched capacitors that store and subtract CMI by control logic. In this paper, a window comparator structure is applied to CMCP to obtain a signal with less distortion. The window voltage ranges were set between the input common-mode ranges in which IA can operate. Therefore, a signal with less distortion was obtained by stopping the operation of CMCP between the window voltage ranges. It also reduced additional current consumption. To achieve this, the proposed circuit is implemented using a chopper stabilization technique. The chopper implemented in the amplifier can reduce low-frequency noise components, such as 1/f noise, and it comprises a CMCP, current feedback instrumentation amplifier, QRS peak detector, relaxation oscillator, voltage reference, timing generator, and serial peripheral interface on a single chip. The proposed circuit was designed using a standard 0.18 μm CMOS process with an active area of 0.54 mm2. The proposed CMCP achieves a CMI robustness of 20 VPP at 60 Hz. The measured input-referred noise level was 119 nV/√Hz at 1 Hz, and the power consumption was 23.83 μW with a 1.8 V power supply.

Current-Feedback Instrumentation Amplifier Using Dual-Chopper Fill-In Technique

In this study, we describe a dual-chopper glitch-reduction current-feedback instrumentation amplifier (CFIA) with a ripple reduction loop. The amplifier employs the chopping technique to reduce low-frequency noise, such as 1/f noise. A glitch caused by chopping occurs at each chopper clock edge and results in intermodulation distortion (IMD). Owing to the input offset, the chopping technique also produces ripples. In this study, the glitch-induced IMD was reduced using a fill-in technique whereby only neat signals were alternately used as outputs by avoiding the glitch section with dual-chopping channel CFIA. To avoid using a high-order, low-frequency filter, a ripple reduction loop was implemented to reduce the ripple generated by chopping. The CFIA is based on a low-noise chopper fully differential difference amplifier with a cascode stage and a Monticelli-class AB output stage, which can drive a larger load and increase power efficiency. The proposed dual-chopper CFIA was fabricated using a 0.18 µm CMOS standard process, and its current consumption with a 1.8-V power supply is 29.5 μA. The proposed CFIA has a gain of 51 V/V, input referred noise of 53.3 nV/√Hz at 1 Hz, and a noise efficiency factor of 4.48.

Low-Noise Resistive Bridge Sensor Analog Front-End Using Chopper-Stabilized Multipath Current Feedback Instrumentation Amplifier and Automatic Offset Cancellation Loop

Resistive bridge sensors are used in many application areas to measure changes in physical parameters. To amplify the resistive changes from sensing elements with high precision, various offset contributors in the resistive bridge and amplifiers should be minimized. This study proposes a low-noise resistive bridge sensor analog front-end (AFE) using a chopper-stabilized multipath current feedback instrumentation amplifier (CFIA) and an automatic offset cancellation loop. The proposed circuit exploits a multipath chopper-stabilized architecture for obtaining low noise performance and wide bandwidth characteristics. This circuit can minimize the offsets in the bridge and the high frequency and low frequency amplifiers, while achieving high precision resistive signal acquisition. The high frequency path of the multipath amplifier uses the CFIA topology with class-AB output stage. The offset in the high frequency path is stabilized by the low frequency path amplifier with a high gain and low noise chopper amplifier. The up-modulated offset in the low frequency chopper amplifier path is reduced by the AC-coupled ripple reduction loop (RRL). An automatic offset calibration loop (AOCL) circuit was designed to calibrate the offset due to the bridge mismatch. The AOCL reduces the bridge offset using a successive approximation register (SAR)-based binary-search algorithm. The gain of the proposed circuit is adjustable from 15.56 dB to 44.14 dB. The AFE is implemented in a <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.18~ \boldsymbol {\mu } \text{m}$ </tex-math></inline-formula> CMOS process and draws <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$123~ \boldsymbol {\mu } \text{A}$ </tex-math></inline-formula> current from a 3.3 V supply. The input referred noise and noise efficiency factor (NEF) are 14.6 nV/ <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\boldsymbol {\surd } $ </tex-math></inline-formula> Hz and 6.1, respectively.

A Low-Power, Low-Noise, Resistive-Bridge Microsensor Readout Circuit with Chopper-Stabilized Recycling Folded Cascode Instrumentation Amplifier

In this paper, a low-power and low-noise readout circuit for resistive-bridge microsensors is presented. The chopper-stabilized, recycling folded cascode current-feedback instrumentation amplifier (IA) is proposed to achieve the low-power, low-noise, and high-input impedance. The chopper-stabilized, recycling folded cascode topology (with a Monticelli-style, class-AB output stage) can enhance the overall noise characteristic, gain, and slew rate. The readout circuit consists of a chopper-stabilized, recycling folded cascode IA, low-pass filter (LPF), ADC driving buffer, and 12-bit successive-approximation-register (SAR) analog-to-digital converter (ADC). The prototype readout circuit is implemented in a standard 0.18 µm CMOS process, with an active area of 12.5 mm2. The measured input-referred noise at 1 Hz is 86.6 nV/√Hz and the noise efficiency factor (NEF) is 4.94, respectively. The total current consumption is 2.23 μA, with a 1.8 V power supply.

Gaussian Process Regression Based Robust Optimization with Observer Uncertainty for Reconfigurable Self-x Sensory Electronics for Industry 4.0

Abstract This paper presents a robust optimization technique for the reconfigurable measurement of sensory electronics for industry 4.0 to obtain a robust solution even in the presence of observer uncertainty using a cost-effective performance measurement method. The extrinsic evaluation of the proposed methodology is performed on an indirect current-feedback instrumentation amplifier (CFIA), which is a fundamental part of sensory systems. To reduce the CFIA device performance evaluation set-up cost, a low-cost test stimulus is applied to the circuit under test, and the output response of the circuit is examined to correlate with the device’s performance parameters. Due to the complexity of the smart sensory electronics search space, the meta-heuristic optimization algorithm is being selected as an optimizer. For objective space or observer uncertainty, the Gaussian process regression from the Bayesian statistical regression process is used to estimate the uncertainty level efficiently. Six different classical metrics have been used to evaluate the regression model accuracy. The highest achieved average expected error metrics value is 0.313, and the minimum value of correlation performance metrics is 0.908. The device is implemented using 0.35 μm austriamicrosystems technology.

Efficient transient testing procedure using a novel experience replay particle swarm optimizer for THD-based robust design and optimization of self-X sensory electronics in industry 4.0

Abstract. This paper aims to improve the traditional calibration method for reconfigurable self-X (self-calibration, self-healing, self-optimize, etc.) sensor interface readout circuit for industry 4.0. A cost-effective test stimulus is applied to the device under test, and the transient response of the system is analyzed to correlate the circuit's characteristics parameters. Due to complexity in the search and objective space of the smart sensory electronics, a novel experience replay particle swarm optimization (ERPSO) algorithm is being proposed and proved a better-searching capability than some currently well-known PSO algorithms. The newly proposed ERPSO expanded the selection producer of the classical PSO by introducing an experience replay buffer (ERB) intending to reduce the probability of trapping into the local minima. The ERB reflects the archive of previously visited global best particles, while its selection is based upon an adaptive epsilon greedy method in the velocity updating model. The performance of the proposed ERPSO algorithm is verified by using eight different popular benchmarking functions. Furthermore, an extrinsic evaluation of the ERPSO algorithm is also examined on a reconfigurable wide swing indirect current-feedback instrumentation amplifier (CFIA). For the later test, we proposed an efficient optimization procedure by using total harmonic distortion analyses of CFIA output to reduce the total number of measurements and save considerable optimization time and cost. The proposed optimization methodology is roughly 3 times faster than the classical optimization process. The circuit is implemented by using Cadence design tools and CMOS 0.35 µm technology from Austria Microsystems (AMS). The efficiency and robustness are the key features of the proposed methodology toward implementing reliable sensory electronic systems for industry 4.0 applications.

A 26 μW area efficient bio-potential acquisition system with feed-forward DC offset cancellation

This paper presents a low-power front-end interface Application Specific Integrated Circuit (ASIC) for bio-potential acquisition. A new feed-forward Direct Current (DC) blocking scheme is proposed for current feedback instrumentation amplifier (CFIA) to reduce the DC electrode offset. The proposed scheme effectively uses an impedance scalar to reduce the size of the capacitor to make it fully on-chip. Apart from electrode offset reduction, chopper stabilization is also utilized for internal offset reduction as well as low-frequency noise removal. Programmable gain and programmable bandwidth units are used to make the interfacing circuit configurable for different type of bio-potentials. A feature extraction channel is included within the interface ASIC to reduce the digital processing overheads for beat detection in Electrocardiogram (ECG) signal processing. The complete circuit is designed and simulated in United Microelectronics Corporation (UMC) 180 nm process technology and the simulation results are presented. Simulation results show that the proposed interface is able to suppress up to 50 mV of DC electrode offset while the total power consumption is 26 μW with a supply of 1.8 V.

A Novel Low Noise Instrumentation Amplifier for Bio-Medical applications

In this work we propose an efficient and a novel Instrumentation amplifier design fabricated using CMOS technology that can be used for the amplification of bio-medical signals. Instrumentation Biological amplifiers play a crucial role in biomedical devices like hearing aids, pacemaker etc. An instrumentation amplifier with current feedback and Current re-use topology along with the Chopper Offset-stabilization technique which was used in op-amps will also be extended to current-feedback instrumentation amplifiers, will help us to minimize and eliminate the flicker (1/f) noise and the offset voltages that will occur during the design of the feedback amplifiers. The gain mismatch problems that usually occurs due to the use of Current re -use topology was also minimized by the use of dynamic element matching technique that will be described in the paper. The design is simulated using Cadence Spectre tool. The Instrumentation amplifier final layout is designed in Cadence Layout editor with 0.18um CMOS technology.

Current-Reused Current Feedback Instrumentation Amplifier for Low Power Leadless Pacemakers

This paper proposes a cardiac electrogram acquisition and stimulation integrated circuit (IC) for single-chamber leadless pacemaker applications. The proposed IC features self-determining pacing by acquiring an intracardiac electrogram without an external digital signal processor (DSP). A novel current-feedback instrumentation amplifier (CFIA) is proposed to achieve high noise-power efficiency and high input impedance. In this proposed CFIA, the current-reused cascode differential-difference input stage and class-AB biasing stage are merged. The electrocardiogram (ECG) sensing channel, equipped with a 60-Hz notch filter to relieve powerline interference (PLI), achieves a power supply rejection ratio (PSRR) of 80 dB, a common-mode rejection ratio (CMRR) of 174 dB, and an input-referred noise of $3.47~\mu $ VRMS, in a 350 Hz bandwidth. The ECG acquisition and cardiac pacing functionality of the IC are evaluated in a swine’s right ventricle via a 4-electrode catheter.

Power Line Interference Reduction Technique with a Current-Reused Current-Feedback Instrumentation Amplifier for ECG Recording

This paper presents a power line interference (PLI) reduction technique with a current-reused current-feedback instrumentation amplifier (CFIA) for electrocardiogram (ECG) recording. In a portable two-electrode ECG monitoring application, the presence of undesired PLI may severely corrupt the quality of ECG recording. Since PLI can be over a few volts, the input signal including the ECG signal can exceed the supply or ground level by an electrostatic discharge (ESD) diode in input/output (I/O) pad. To prevent this problem, this paper presents a continuous-time input common-mode current feedback loop that can limit displacement current from a capacitive coupling between the human body and a power line. The continuous-time input common-mode current feedback loop can clamp an input common-mode voltage to the saturation region of the input transistor of the current-reused CFIA. After the clamping procedure, the clamped input signal is amplified by the current-reused CFIA. The proposed circuit was designed using a 0.18-μm bipolar-complementary metal semiconductor–double-diffused metal oxide semiconductor (BCDMOS) process with an active area of 1.8 mm2. The total power consumption is 18 μW with 1.8 V. The input-referred noise and noise efficiency factor (NEF) of the current-reused CFIA is 2.68 μVRMS and 4.28 with 107 Hz, respectively.

Current Feedback Instrumentation Amplifier With Built-In Differential Electrode Offset Cancellation Loop for ECG/EEG Sensing Frontend

This work describes a compact and low-power current feedback instrumentation amplifier (CFIA) that can effectively eliminate differential electrode offset (DEO), amplifier input offset, and light motion artifacts. The proposed approach is using a local feedback loop in the first stage of the CFIA which can eliminate dc and low frequency offset whereas by-passes useful components such as EEG and ECG signals. As a result, the DEO and amplifier input offset can be eliminated in the first stage of the CFIA while still amplifying the desired signal components. This enables offset cancellation operation with low bias current that leads to higher energy efficiency compared to existing CFIA offset cancellation schemes. The proposed CFIA is implemented using CMOS 0.18-μm technology, that can eliminate up to 250-mV DEO with a supply voltage of 1.8 V. Measurement results show common mode rejection ratio (CMRR) 120 dB (without DEO) and 95 dB (with DEO of 250 mV) at 10 Hz, input noise 3.8 μVrms, power consumption 12.7 μW, and NEF 39 with core area of 73.6 × 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-3</sup> mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . Furthermore, the actual EEG and ECG waveforms are obtained using the proposed CFIA under an actual clinical setting.

Reconfigurable Wide Input Range, Fully-Differential Indirect Current-Feedback Instrumentation Amplifier with Digital Offset Calibration for Self-X Measurement Systems

Abstract This manuscript presents an implementation of the configurable indirect current-feedback instrumentation amplifier (CFIA) for sensor interface readout circuit. Configuration is achieved by designing digital weighted scalable arrays for some selected elements to serve as tuning knobs controlled by the evolutionary optimization algorithm. This scheme resulting in a programmable circuit for different aspects to support self-x functionality. The robustness and flexibility of the proposed circuit fit to the demands of measurement and sensory systems in industry 4.0 and other intelligent systems applications. The circuit is designed by Cadence tools using ams 0.35 μm CMOS technology.

Low-cost Indirect Measurement Methods for Self-x Integrated Sensory Electronics for Industry 4.0

AbstractThe conventional method for testing the performance of reconfigurable sensory electronics of industry 4.0 relies on the direct measurement methods. This approach gives higher accuracy but at the price of extremely high testing cost and does not utilize the new degrees of freedom for measurement methods enabled by industry 4.0. In order to reduce the test cost and use available resources more efficiently, a primary approach, called indirect measurements or alternative testing has been proposed using a non-intrusive sensor. Its basic principle consists in using the indirect measurements, in order to estimate the sensory electronics performance parameters without measuring directly. The non-intrusive property of the proposed method offers better performance of the sensing electronics and virtually applicable to any sensing electronics. Efficiency is evaluated in terms of model accuracy by using six different classical metrics. It uses an indirect current-feedback instrumentation amplifier (InAmp) as a test vehicle to evaluate the performance parameters of the circuit. The device is implemented using CMOS 0.35 μm technology. The achieved maximum value of average expected error metrics is 0.24, and the lowest value of correlation performance metrics is 0.91, which represent an excellent efficiency of InAmp performance predictor.

A Low-Noise Area-Efficient Current Feedback Instrumentation Amplifier

The low-power current feedback instrumentation amplifier (CFIA) circuits using local feedback configuration are reported in the literature for biomedical applications. However, they have limitations such as low gain, higher area, and higher noise due to the need for higher source degeneration resistors (in tens to hundreds of kΩ), and higher minimum achievable bandwidth (in tens of kHz). In this paper, a low-power, low-noise CFIA using closed-loop configuration is proposed to overcome these limitations. It uses a folded cascode operational transconductance amplifier with a lower value of source degeneration resistor (in the order of few kΩ) in the input stage to reduce the noise without compromising the loop gain. As the bandwidth of the proposed CFIA is defined as unity-gain bandwidth of the CFIA’s loop gain, it can be reduced below 10 kHz without increasing area. The proposed CFIA is designed and implemented in a 0.35 µm CMOS process for a current of 9.6 µA with a supply voltage of 3 V, and its performance is evaluated through simulation. It has a gain of 34 dB, total input-referred noise of 3 µVrms, and a noise efficiency factor of 3.81. It achieves a bandwidth of 8.8 kHz using a load capacitor which is more than four times smaller than that of local CFIA. It provides an input signal swing of 16 mVpp at THD of 1% and the CMRR of 118 dB.

Fully Differential Chopper-Stabilized Multipath Current-Feedback Instrumentation Amplifier with R-2R DAC Offset Adjustment for Resistive Bridge Sensors

A fully differential multipath current-feedback instrumentation amplifier (CFIA) for a resistive bridge sensor readout integrated circuit (IC) is proposed. To reduce the CFIA’s own offset and 1/f noise, a chopper stabilization technique is implemented. To attenuate the output ripple caused by chopper up-modulation, a ripple reduction loop (RRL) is employed. A multipath architecture is implemented to compensate for the notch in the chopping frequency band of the transfer function. To prevent performance degradation resulting from external offset, a 12-bit R-2R digital-to-analog converter (DAC) is employed. The proposed CFIA has an adjustable gain of 16–44 dB with 5-bit programmable resistors. The proposed resistive sensor readout IC is implemented in a 0.18 μm complementary metal-oxide-semiconductor (CMOS) process. The CFIA draws 169 μA currents from a 3.3 V supply. The simulated input-referred noise and noise efficiency factor (NEF) are 28.3 nV/√Hz and 14.2, respectively. The simulated common-mode rejection ratio (CMRR) is 162 dB, and the power supply rejection ratio (PSRR) is 112 dB.

Wide input range, fully-differential indirect current feedback instrumentation amplifier for self-x sensory systems / Symmetrischer Instrumentierungsverstärker mit indirekter Stromgegenkopplung und hoher Eingangsignalspanne für integrierte Sensorsysteme mit Self-x-Eigenschaften

Abstract This paper research presents the design of wide input range indirect current feedback-instrumentation amplifier (CFIA). In order to extend the input range without sacrificing the amplifier performance, the negative feedback is applied to the source coupled differential pairs inputs. The feedback network and the biasing current can be programmed to work at different values to meet different signal conditions or to self-correct the drift in the amplifier properties. The simulated input range Vin; P-P=1.6 V with total harmonic distortion of 0.93 % at 5 MHz frequency. Thus the proposed CFIA is very suitable to read the high speed and high common mode range TMR differential voltage sensor signal. The circuit is implemented using the CMOS 0.35 μm technology from Austriamicrosystems (AMS) and by using Cadence Virtuoso design tools.