Cu-filled Through Silicon Via Research Articles

(Invited) Through-Silicon Via Copper Plating and Endpoint Detection

Heterogenous, 2.5D, and 3D integration provide solutions for making microelectronics systems more compact and improving their performance. Cu-filled through-silicon vias (TSVs) are an important interconnect technology for these advanced integration techniques. TSV design and geometry (overall size, aspect ratio, and pitch) depend on the intended microelectronics application. Standard integrated circuit (IC) approaches often utilize high density vias that are achieved through substrate thinning; however, some applications need large-scale vias (≥ 600 µm deep). For example, some microelectromechanical systems (MEMS) applications need full wafer thickness vias due to die thickness specifications, and high-power devices can either employ large-scale vias or via arrays for current requirements and thermal management constraints. Cu deposition fill profile is sensitive to applied voltage or current, electrolyte composition and concentrations, and feature geometry; therefore, deposition processes must be tuned specifically for each via geometry. This work outlines Cu deposition process development and filling results for full wafer thickness TSV geometries in a suppressor-based electrolyte consisting of copper sulfate, sulfuric acid, potassium chloride, and Tetronic 701 suppressor, [i] according to the S-shaped Negative Differential Resistance (S-NDR) mechanism. [ii],[iii] During these TSV filling experiments, unique features in the electrical data were observed that signify completion of Cu plating in the vias. A novel endpoint detection method was derived from these data to determine when vias are filled. [i] Analogous endpoint detection through electrical signals has been previously observed for bottom-up Au filling of high aspect ratio trenches. [iv] During voltage-controlled via filling, as the Cu electrodeposit approaches the top of the TSVs, current can be monitored for a slight rise (due to increased metal ion transport and plating rate high up in the features), followed by a current local minimum (caused by adsorbed suppressor molecules that impede Cu deposition at the top of the vias). These characteristic features in the electrical data can be used to determine via filling completion. A similar technique can be used during current-controlled filling, where voltage data are monitored for a voltage maximum, which indicates that the Cu electrodeposit has reached the top of the features. Current work involves development of an automated method to recognize these electrical endpoint signals and terminate deposition when the vias are filled. This endpoint detection method has potential to greatly enhance microelectronics manufacturing by providing geometry-independent process control, improving manufacturing repeatability, decreasing sensitivity to changes in electrolyte over time, and reducing the time involved in subsequent processing steps through minimizing Cu overburden formation.Sandia National Laboratories is a multimission laboratory managed and operated by National Technology and Engineering Solutions of Sandia, LLC., a wholly owned subsidiary of Honeywell International, Inc., for the U.S. Department of Energy’s National Nuclear Security Administration under contract DE-NA-0003525. SAND2021-5013 A [i] R. P. Schmitt et al 2020 J. Electrochem. Soc. 167 162517. [ii] D. Josell and T. P. Moffat 2016 ECS Trans. 75 15. [iii] D. Josell and T. P. Moffat 2018 J. Electrochem. Soc. 165 D23. [iv] S. Ambrozik et al 2019 J. Electrochem. Soc. 166 D443.

Stress Impact of the Annealing Procedure of Cu-Filled TSV Packaging on the Performance of Nano-Scaled MOSFETs Evaluated by an Analytical Solution and FEA-Based Submodeling Technique.

Stress-induced performance change in electron packaging architecture is a major concern when the keep-out zone (KOZ) and corresponding integration density of interconnect systems and transistor devices are considered. In this study, a finite element analysis (FEA)-based submodeling approach is demonstrated to analyze the stress-affected zone of through-silicon via (TSV) and its influences on a planar metal oxide semiconductor field transistor (MOSFET) device. The feasibility of the widely adopted analytical solution for TSV stress-affected zone estimation, Lamé radial stress solution, is investigated and compared with the FEA-based submodeling approach. Analytic results reveal that the Lamé stress solution overestimates the TSV-induced stress in the concerned device by over 50%, and the difference in the estimated results of device performance between Lamé stress solution and FEA simulation can reach 22%. Moreover, a silicon–germanium-based lattice mismatch stressor is designed in a silicon p-type MOSFET, and its effects are analyzed and compared with those of TSV residual stress. The S/D stressor dominates the stress status of the device channel. The demonstrated FEA-based submodeling approach is effective in analyzing the stress impact from packaging and device-level components and estimating the KOZ issue in advanced electronic packaging.

Role of Grain Boundary Sliding in Structural Integrity of Cu-Filled Through Si Via During Isothermal Annealing

Herein, annealing experiments were performed on Cu-filled through silicon via (Cu-TSV) samples in the temperature range of 250–550°C and the relevant microstructural aspects were examined using scanning electron microscope, electron back-scattered diffraction (EBSD) and crystal plasticity (CP) simulations to study the role of grain boundary sliding in Cu on the structural integrity of Cu-TSV. Grain boundary sliding induced non-uniform extrusion of the Cu, as recognized by the formation of vertical steps at the boundaries of Cu grains, was observed in all samples. EBSD of the Cu surface revealed that a group of randomly oriented grains slid relative to each other. CP simulations indicated generation of large shear stresses along the grain boundaries of Cu during annealing that can drive grain boundary sliding. Furthermore, CP simulations also suggested a limited effect of the crystallographic texture of Cu on the plasticity induced extrusion of Cu relative to Si. Finally, grain boundary sliding induced non-uniform extrusion of Cu continued to occur at the highest annealing temperature; however, it could not efficiently relax the thermal stresses and micro-cracks nucleated in Si. This study, therefore, confirms the important role of grain boundary sliding in the stress relaxation and the structural integrity of Cu-TSV samples.

Study of the Influence of Elastic Anisotropy of Cu on Thermo-Mechanical Behavior and Cu Protrusion of Through Silicon Vias Using Combined Phase Field and Finite Element Methods

Drastic reduction in the diameter of the Cu-filled through silicon via (TSV) leads to the TSV feature size becoming comparable with the grain size in the Cu filler, and accordingly Cu grain characteristics strongly influence thermo-mechanical behavior and Cu protrusion of the TSV due to the elastic anisotropy of Cu, which poses new emerging issues and challenges for reliability analysis of the TSV. In this paper, a 2-D phase field model is combined with a finite element model to study comprehensively and quantitatively the grain morphology characteristics, thermo-mechanical behavior and Cu protrusion in a typical Cu-filled TSV structure, while considering the mechanical property anisotropy of Cu. Results show that Cu grains with different orientations make distinct contributions to the deformation behavior of the Cu filler which undergoes three stages of deformation, that is, elastic, elasto-plastic, and plastic as temperature increases, consequently resulting in the anisotropic thermo-mechanical behavior of the Cu-filled TSV and the dependence of Cu protrusion on the average grain size of the Cu filler. Moreover, both the average von Mises stress and equivalent plastic strain of the Cu filler decrease with the increase in Cu grain size, and the average von Mises stress in fine grains is higher than that in coarse grains. Furthermore, Cu protrusion decreases with the increase of the average size of Cu grains. However, for limited grains in the Cu-filled TSV, the average von Mises stress, equivalent plastic strain, and Cu protrusion increase with an increase in the average size of Cu grains.

Effect of Thermal Mechanical Behaviors of Cu on Stress Distribution in Cu-Filled Through-Silicon Vias Under Heat Treatment

Through-silicon vias (TSV) are facing unexpected thermo-mechanical reliability problems due to the coefficient of thermal expansion (CTE) mismatch between various materials in TSVs. During applications, thermal stresses induced by CTE mismatch will have a negative impact on other devices connecting with TSVs, even leading to failure. Therefore, it is essential to investigate the stress distribution evolution in the TSV structure under thermal loads. In this report, TSVs were heated to 450°C at different heating rates, then cooled down to room temperature after a 30-min dwelling. After heating treatment, TSV samples exhibited different Cu deformation behaviors, including Cu intrusion and protrusion. Based on the different Cu deformation behaviors, stress in Si around Cu vias of these samples was measured and analyzed. Results analyzed by Raman spectrums showed that the stress distribution changes were associated with Cu deformation behaviors. In the area near the Cu via, Cu protrusion behavior might aggravate the stress in Si obtained from the Raman measurement, while Cu intrusion might alleviate the stress. The possible reason was that in this area, the compressive stress $$ \sigma_{\theta }$$ induced by thermal loads might be the dominant stress. In the area far from the Cu via, thermal loads tended to result in a tensile stress state in Si.

Statistical Distribution of Through-Silicon via Cu Pumping

Cu pumping is defined as the irreversible extrusion of Cu from Cu-filled through-silicon vias (TSVs) exposed to high temperatures. The distribution of Cu pumping values over the TSVs of a single wafer has a large intrinsic spread. In previous publications both a lognormal distribution and a distribution of the maximum of two normal variables were used to fit experimental data. In this paper, these two types of statistical distribution are compared, showing that the maximum of two normal distributions provides a better fit, in particular at the right tail which is more significant for the potential reliability impact of Cu pumping. Also, it is shown how Cu pumping is determined by the network of random high angle grain boundaries in the Cu region near the TSV top, as an extension of a previous analysis which occurred at the TSV top surface only. This relation between Cu pumping and Cu microstructure provides a physical interpretation of the maximum of two normal distributions, based on the deformation mechanisms underlying Cu pumping.

Microstructure Evolution and Protrusion of Electroplated Cu-Filled Through-Silicon Vias Subjected to Thermal Cyclic Loading

Through-silicon vias (TSVs) have become an important technology for three-dimensional integrated circuit (3D IC) packaging. Protrusion of electroplated Cu-filled vias is a critical reliability issue for TSV technology. In this work, thermal cycling tests were carried out to identify how the microstructure affects protrusion during thermal cycling. Cu protrusion occurs when the loading temperature is higher than 149°C. During the first five thermal cycles, the grain size of Cu plays a dominant role in the protrusion behavior. Larger Cu grain size before thermal cycling results in greater Cu protrusion. With increasing thermal cycle number, the effect of the Cu grain size reduces and the microstrain begins to dominate the Cu protrusion behavior. Higher magnitude of microstrain within Cu results in greater protrusion increment during subsequent thermal cycles. When the thermal cycle number reaches 25, the protrusion rate of Cu slows down due to strain hardening. After 30 thermal cycles, the Cu protrusion stabilizes within the range of 1.92 μm to 2.09 μm.

Effects of dimension parameters and defect on TSV thermal behavior for 3D IC packaging

Through Silicon Via (TSV) technology is a promising and preferred way to realize the reliable interconnection for 3D IC integration. The temperature changed in the processes of TSV manufacturing and chip using, due to the mismatch in the Coefficient of Thermal Expansion (CTE) of the materials used in TSV structure, significant thermal stress will be induced under the thermal load. These stresses may lead to various reliability issues. Dimension parameters and defects are the two factors affecting the thermal behavior of TSV. In order to optimize TSV design and the quality of via filling, a numerical model of Cu-filled TSV was established to simulate and analyze the effect of diameter, aspect ratio (AR) and defects on TSV thermal stress and deformation in this paper. Simulation results show that the equivalent stress and total deformation of TSV increases as the increase of the diameter of TSV. The effect of aspect ratio on equivalent stress is very little; however, it has a great impact on total deformation, especially for the large diameter of the TSV. Additionally, the effects of shape, size and location of defect on thermal stress were also investigated.

On the origins of near-surface stresses in silicon around Cu-filled and CNT-filled through silicon vias

Micro-Raman spectroscopy was employed to study the near-surface stress distributions and origins in Si around through silicon vias (TSVs) at both room temperature and elevated temperatures for Cu-filled and carbon nanotube (CNT)-filled TSV samples. From observations, we proved that the stresses near TSVs are mainly from two sources: (1) pre-existing stress before via filling, and (2) coefficients of thermal expansion (CTE) mismatch-induced stress. CTE-mismatch-induced stress is shown to dominate the compressive regime of the near-surface stress distribution around the two types of Cu-filled TSV structures in this work and in previous work, while pre-existing stress dominates the full range of the stress distribution in the CNT-filled TSV structures studied. These results show the importance of the pre-existing stress and support the use of a liner technology with lower stress introduction such as deposited oxide instead of thermal oxide. It is specifically important for CNT-filled TSVs, where the pre-existing stress is much larger than the CTE-mismatch-induced stress as observed in this work.

Induced thermo-mechanical reliability of copper-filled TSV interposer by transient selective annealing technology

Managing the stability of related processes in the integrated manufacturing of three-dimensional integrated circuits (3D-ICs) remains unresolved, especially with regard to the thermo-mechanical behavior of copper filled through silicon via (TSV) interposer during annealing. In this work, transient annealing is successfully applied on the filled copper using only one form of selective heating technology. To address the integration problem, transient thermo-structural coupling analysis using a nonlinear finite element simulation is proposed. Compared with the experimental data, the proposed simulation is found to be highly reliable. Analytical results show that temperature decreases from the top surface of the TSV to other regions within a silicon-based TSV interposer. Stress-induced fracture is common among bonded films, thereby worsening the subsequent mechanical reliability of 3D-IC devices. Moreover, the extent of keep-out zone induced by residual stress of Cu-filled TSV is also defined through the simulation-based mobility gain of nano-scaled devices. In accordance with the results of this investigation, an improvement can be obtained by optimizing the fabrication parameters during annealing. The proposed technology provides a high throughput and reliable processes in TSV manufacturing.

Extrusion Suppression of TSV Filling Metal by Cu-W Electroplating for Three-Dimensional Microelectronic Packaging

Extrusion behavior of Cu filling in through-silicon-via (TSV) under thermal loading was investigated in this study. In order to suppress the extrusion of Cu-filled TSV, Cu-W was filled in a tapered TSV by electroplating. The Cu-filled TSV was used as a reference for comparison. Defect less filling of Cu-W in TSV was achieved at a composition 92.4 wt pct Cu and 7.6 wt pct W. The coefficients of thermal expansion of both Cu-7.6 pctW and Cu were 10.8 × 10−6/°C and 16.5 × 10−6/°C, respectively. Initially, both Cu and Cu-W filled TSVs were annealed for 30 minutes at 723 K (450 °C) and the extrusion heights were measured. The results showed that the extrusion of Cu-W filled was suppressed significantly compared to Cu-filled TSVs. The annealed extrusion heights of Cu and Cu-W were found to be 1.369 and 0.465 µm, respectively. This showed around 34 pct lower extrusion height of Cu-W filled TSV as compared to Cu-filled TSV. The extrusion kinetics with different annealing durations and the mechanism of the suppression of extrusion in Cu-W filled TSV are also reported here.

Effect of Current Density and Plating Time on Cu Electroplating in TSV and Low Alpha Solder Bumping

In this study, copper filling in through-silicon via (TSV) by pulse periodic reverse electroplating and low alpha solder bumping on Cu-filled TSVs was investigated. The via diameter and depth of TSV were 60 and 120 µm, respectively. The experimental results indicated that the thickness of electrodeposited copper layer increased with increasing cathodic current density and plating time. The electroplated Cu in TSV showed a typical bottom-up filling. A defectless, complete, and fast 100% Cu-filled TSV was achieved at cathodic and anodic current densities of −8 and 16 mA/cm2 for a plating time of 4 h, respectively. A sound low alpha solder ball, Sn-1.0 wt.% Ag-0.5 wt.% Cu (SAC 105) with a diameter of 83 µm and height of 66 µm was reflow processed at 245 °C on Cu-filled TSV. The Cu/solder joint interface was subjected to high temperature aging at 85 °C for 150 h, which showed an excellent bonding characteristic with minimum Cu-Sn intermetallic compounds growth.

Analysis of the electrical characteristics and structure of Cu-Filled TSV with thermal shock test

The electrical characteristics and failure of a Through-Silicon Via (TSV) were investigated using a thermal shock test. The electrical characteristics, such as resistance (R), self-inductance (Ls), self-capacitance (Cs), and mutual capacitance (Cm), were extracted using a T-equivalent circuit. A cross section of the Cu-filled via was observed by field emission-scanning electron microscopy and the electrical characteristics were measured using a commercial Agilent E4980A LCR Meter. The experimental results revealed R, Ls, Cs, and Cm values of 3.2 mΩ, 29.3 pH, 12 fF, and 0.42 pF, respectively. Cm occurred between the charge-holding TSVs, which changed from 0.42 pF to 0.26 pF due to a permittivity transition of the Cu ion drift. After 1,000 cycles of a thermal shock test, cracks were observed between the opening and around the side of the TSV and Si wafer due to mismatch of the coefficient of thermal expansion between the Cu-plug and Si substrate.

Energy Release Rate Estimation for Through Silicon Vias in 3-D IC Integration

The technology of 3-D IC integration is expected to satisfy the demand for high-performance, better reliability, miniaturization, and lower priced portable electronic products. Since through silicon via (TSV) is at the heart of 3-D IC integration architectures, the reliability issues with TSV interconnects are an area of extreme concern. Due to the large thermal expansion mismatch among the copper (Cu), silicon die, and silicon dioxide (SiO2) dielectric layer, the induced thermal stresses and strains can occur and become the driving forces that cause failures in TSV interconnects. Hence, thermomechanical stress analyses and failure mode investigations for TSVs are in urgent need. Among the typical failures, delamination is the mostly common failure type, which is caused when lower energy release rate (ERR) or higher critical stresses at interfaces are present. In this paper, the finite element analysis (FEA) for a symmetrical single inline Cu-filled TSV with redistribution layer is illustrated and has been used to realize the thermomechanical stress distribution for TSVs in 3-D IC integration. Moreover, four kinds of interfacial cracks that were embedded in the interface of SiO2 passivation and Cu seed layer (Cu pad and TSV wall delamination cases) and the critical stress areas observed from FEA are introduced to estimate the interfacial ERR using modified virtual crack closure technique. The parametric study has also been adopted to capture the most important mechanical factors of the TSVs to comprehend the corresponding ERR. The significance of discussed parameters such as crack length, TSV diameter, TSV pitch, TSV depth, SiO2 thickness, and Cu seed layer thickness are also examined. It is believed that these results would be helpful to avoid delamination of TSV interconnects in 3-D IC integration.

Electrical characteristics and thermal shock properties of Cu-filled TSV prepared by laser drilling

The electrical characteristics and thermal shock properties of a Through Silicon Via (TSV) for the three dimensional (3D) stacking of a Si wafer were investigated. The TSVs were fabricated on a Si wafer by a laser drilling process. The via had a diameter of 75 µm at the via opening and a depth of 150 µm. A daisy chain was made for testing electrical characteristics, such as Rsh (sheet resistance), Rc (contact resistance) and Z0 (characteristic impedance). After Cu filling, a cross section of the via was observed by Field Emission-Scanning Electron Microscopy. The electrical characteristics were measured using a commercial impedance analyzer and probe station, which revealed the values of Rsh, Rc and Z0 as 35.5 mΩ/sq, 25.4 mΩ and 48.5 Ω, respectively. After a thermal shock test of 500 cycles, no cracks were observed between the TSV and Si wafer. This study confirms that the laser drilling process is an effective method for via formation on a Si wafer for 3D integration technology.

Impact of high density TSVs on the assembly of 3D-ICs packaging

Multi-scale modeling construction and subsequent stress analysis for the mechanical reliability estimation of three-dimensional (3D) integrated circuit (IC) packages is challenging. This paper presents a simulation-based methodology to calculate the equivalent mechanical properties of 3D-ICs through-silicon via (TSV) interposer composed of silicon chip and copper (Cu)-filled metal to resolve this difficulty. The obtained material properties can be utilized in non-concerned regions of analytic structure to reduce modeling complexity significantly and preserve the predicted accuracy in critical locations of 3D-IC packaging simultaneously. The verification of the corresponding analytical solutions ascertains the high reliability of the results predicted by the proposed approach. The results indicate that TSV pitch is a key design factor that dominates the characteristic of a silicon interposer with array-type Cu-filled TSV. The effect resulting from TSV can be ignored as the pitch exceeds 40@mm, and pure silicon interposer is assumed to exhibit an isotropic behavior in the related stress assessment using finite element analysis.

Understanding and Controlling Cu Protrusions in 3D TSV Processing

Cu-filled through-silicon vias (TSVs) are an essential building block of 3D and 2.5D integrated chips. In the TSV-mid processing flow, which has emerged as an industry mainstream, one or more on-chip wiring levels are formed after the TSV Cu fill is completed, which exposes the fill to peak temperatures of up to 400 °C. Due to the higher coefficient of thermal expansion (CTE) of Cu than the surrounding silicon and dielectrics, the TSV fill protrudes above the level previously defined by the TSV chemical mechanical polishing (CMP) step. Even after returning to room temperature, the top of the TSV will not occupy the same space due to plastic deformation during the thermal treatment. This phenomenon is known as Cu protrusions, pumping, or popping. Excessive amounts of Cu protrusion present a risk to yields and reliability because the expansion can damage dielectrics and wiring above or adjacent to the TSVs. In this study, we report the underlying mechanisms as well as process remedies for Cu protrusions. The SEMATECH 5 um × 50 um TSV process and learning vehicle is used to conduct process split experiments comparing various plating chemistries, plating recipes, and post-plating anneal conditions. Stresses in the surrounding silicon are studied by micro-Raman, and a distinct signature distinguishing good from bad Cu protrusion behavior is identified. Cu material properties such as contamination, grain size, grain orientation, and strain may also influence the protrusion behavior; these factors are studied by micro-secondary ion mass spectroscopy (SIMS) and electron backscatter spectroscopy (EBSD). Our results shows that the choice of plating chemistry and subsequent optimized post-plating anneal are the main factors in suppressing Cu protrusions. Our best known method is able to reduce Cu protrusions to about 15 nm after typical thermal loads.

Thermal Stress and Creep Strain Analyses of a 3D IC Integration SiP with Passive Interposer for Network System Application

In this study, the nonlinear thermal stress distributions at the Cu-low-k pads of Moore's law chips and creep strain energy density per cycle at the solder joints of a 3D IC integration system-in-package (SiP) are investigated. At the same time, the warpage of the TSV interposer and reliability assessment of solder joints in the architecture is examined. The analyzed structure comprises one PCB (printed circuit board), one BT (bismaleimide triazene) substrate, one interposer with through silicon vias (TSVs), two DRAM (dynamic random access memory) chips and one high power ASIC (application specific integrated circuit) chip. The high power chip and DRAM chips are supported, respectively on the top-side and bottom-side of the Cu-filled TSV interposer.

Oxide Liner, Barrier and Seed Layers, and Cu Plating of Blind Through Silicon Vias (TSVs) on 300 mm Wafers for 3D IC Integration

In this study, key enabling technologies such as the oxide liner by the PECVD, the barrier and seed layers by the PVD, and Cu plating of blind TSVs on 300 mm wafers for 3D integration are investigated. Emphasis is placed on the determination and optimization of the important parameters for each of the key enabling technologies. Also, the leakage current of the fabricated Cu-filled TSVs is measured. Furthermore, cross sections and SEM of the fabricated TSVs are examined.

Elastic anisotropy of Cu and its impact on stress management for 3D IC: Nanoindentation and TCAD simulation study

Abstract