Abstract
The electrical characteristics and thermal shock properties of a Through Silicon Via (TSV) for the three dimensional (3D) stacking of a Si wafer were investigated. The TSVs were fabricated on a Si wafer by a laser drilling process. The via had a diameter of 75 µm at the via opening and a depth of 150 µm. A daisy chain was made for testing electrical characteristics, such as Rsh (sheet resistance), Rc (contact resistance) and Z0 (characteristic impedance). After Cu filling, a cross section of the via was observed by Field Emission-Scanning Electron Microscopy. The electrical characteristics were measured using a commercial impedance analyzer and probe station, which revealed the values of Rsh, Rc and Z0 as 35.5 mΩ/sq, 25.4 mΩ and 48.5 Ω, respectively. After a thermal shock test of 500 cycles, no cracks were observed between the TSV and Si wafer. This study confirms that the laser drilling process is an effective method for via formation on a Si wafer for 3D integration technology.
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