Crosspoint Faults Research Articles

Fault detection in multiple controlled Fredkin circuits

Testing is an essential process to validate the truthful functionality of logic circuits, devices, and systems. It accounts a large overhead in terms of additional hardware, time, and manpower which dramatically enhance overall cost of manufacturing. The efficacy of multiple control Fredkin (MCF) gates towards both online and offline testing paradigms is demonstrated here by exploiting their parity preserving and conservative properties. The authors introduce (i) a method of testing MCF circuits for the detection of bit-flip faults online; (ii) deterministic approaches for the identification of stuck-at, bridging, missing gate, and cross-point faults; and (iii) three test sets of size 2, n, and for the detection of these faults off-line. Experiments are performed on a set of benchmarking circuits to demonstrate the effectiveness of the proposed methods in terms of test overhead and fault coverage. Online testable circuits are formulated on account of 0.5% of overhead in terms of considered cost metrics and an average reduction up to 61% is calculated with respect to existing work in the area. The test sets show completeness for the detection of all considered fault models. Fault simulations for both the presented testing methodologies are carried out which shows 100% coverage.

An interconnected multi-plane multi-stage fault-tolerant on-board switching fabric

The harsh space radiation environment compromises the reliability of an on-board switching fabric by leading to cross-point and switching element (SE) faults. Different from traditional fault-tolerant switching fabrics only taking cross-point faults into account, a novel Input and Output Parallel Clos network, referred to as the (p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ,p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )-IOPClos, is proposed to tolerate both cross-point and SE faults. In the (p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ,p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )-IOPClos, there are p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> and p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> expanded parallel switching planes in the input and output stages, respectively. The multiple input/output switching planes are interconnected through the middle stage to provide multiple paths in each stage by which the network throughput can be increased remarkably. Furthermore, the network reliability of the (p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ,p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )-IOPClos under the above both kinds of faults is analyzed. The corresponding implementation cost is also presented along with the network size. Both theoretical analysis and numerical results indicate that the (p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ,p <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> )-IOPClos outperforms traditional Clos-type networks at reliability, while has less implementation cost than the multi-plane Clos network.

A graph representation for programmable logic arrays to facilitate testing and logic design

In this paper, we present a new graph model and an associated set of operations for representing programmable logic arrays (PLAs). The signal lines and devices of a PLA are represented as the edges and vertices of a directed graph, respectively. Through this graph model, most realistic PLA faults, including cross-point, stuck-at, break, and bridging faults, can be modeled and classified, and the maximal diagnosis resolution of a PLA can be determined. Moreover, the model can be easily transformed into a gate-level model. Hence, the work of automatic test-pattern generation for a PLA and for other random logic ran be done simultaneously. We also show that this representation can be extended to some logic design techniques such as logic minimization, folding, and decomposition for PLAs. Thus, this graph model can unify the data structure and operations required in PLA design and test.

Low test-application time method for EEPLA testing

An efficient method for EEPLA testing is presented. In this method the authors propose an interleave programming algorithm for the EEPLA to enhance the controllability of the OR plane and the observability of the AND plane during the testing of EEPLA. The salient features of this method are: (i) low overhead, (ii) high fault coverage, (iii) simple test set, and (iv) low test-application time. Using this method, all multiple stuck-at faults, multiple crosspoint faults and all multiple bridging faults can be detected.

EARTH: combined state assignment of PLA-based FSM's targeting area and testability

Stuck-at and crosspoint faults in PLA's introduce combinational and sequential redundancies in PLA-based FSM's that affect the testability of these FSM's. We propose a new state assignment algorithm for PLA-based FSM's called EARTH that simultaneously considers area minimization and testability of the resultant PLA's. Our fault model is the single stuck-at and/or single crosspoint fault model. Experimental results show that, on an average, the number of undetectable faults which result due to state assignment by EARTH is about five times less than those generated due to state assignment by NOVA with area overhead 2% more than NOVA.

Fault analysis and automatic test pattern generation for break faults in programmable logic arrays

The conventional fault models of PLAs are crosspoint, stuck-at and bridging fault models. Many techniques for PLA testing based on these fault models have been proposed in the past. However, these techniques cannot be applied to the break fault model due to the memory behaviour. Unfortunately, it has been shown that break faults occur frequently. Thus, considering a break fault model is important to enhance the quality of PLA testing. The behaviour of break faults in PLAs is analysed in detail and a complete PLA break fault ATPG system, PLABEK, is proposed. PLABEK contains four main parts: break fault collapsing: pruning algorithm based test pair generation; serial-fault-injection parallel-bit-operation event-driven break fault simulation; and testability-measure-based fault ordering. Experimental results show that PLABEK can generate very compact complete test sequences for break faults of PLAs very fast.

A new testing method for EEPLA

A testing method for EEPLA's is presented. The method requires small amount of extra hardware and provides complete fault coverage. This method exploits the fact that each crosspoint can be reprogrammed in EEPLA. To our knowledge, this is the first algorithmic test method applicable to EEPLA's. In the proposed approach, all single and multiple crosspoint faults, stuck-at faults, and bridging faults are detectable. The test set is simple and is easy to derive.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

FSMTEST: synthesis for testability and test generation of PLA-based FSM

A new hardware scheme for easily testable PLA-based finite state-machines is proposed. With this scheme, all combinationally nonredundant crosspoint faults in the PLA logic implementation are testable. Moreover, test generation is easily accomplished because short systematic initialisation sequences exist for each internal state in the machine and unit length distinguishing sequences, which hold under the faulty condition existing for every true faulty state pair. The authors present an outline of the proposed scheme, which consists basically of the addition of some state transitions and their output to the state transition graph (STG) of the machine. A test generation procedure is described which requires neither fault simulation nor manipulation of the machine's STG.

Finite state machine synthesis with fault tolerant test function

According to a recent synthesis for testability proposal, a test function specified as a finite state machine with the same number of state variables as the given object machine, is incorporated into the state diagram prior to synthesis. Since a complete verification of the test machine is not practical, an often used heuristic sets and observes each state variable. The two machines share logic and a fault can result in partial or total loss of the test function. We show that the tests generated under the assumption that the entire test function is intact can become invalid. We propose a new method of synthesizing PLA-based finite state machines with fault tolerant test machines. Our approach eliminates testing of the test function. A constrained logic minimization phase insures that faults have predictable effect on the state diagram of the composite machine (object machine embedded with the test function). This allows effective use of the test function during test generation even in the presence of faults that effect both object and test machines. Only a combinational test generator is required for test generation. Each combinational vector is augmented by appropriate initialization and propagation sequences. Unlike prior approaches, ourO(log2 n) length test sequence isguaranteed to detect any targeted crosspoint fault. Experimental results on the MCNC Logic Synthesis Workshop finite state machine benchmark set are given as evidence of practicality of the proposed approach.

The OR-k method for on-line checking of programmable logic arrays

A programmable logic array (PLA) is nonconcurrent if every input pattern selects exactly one product term. We relax this requirement to limited concurrency where all product terms selected by the same input pattern must have identical output parts. A new testing method, OR-k testability, is developed for the on-line (concurrent) checking of limited concurrency PLAs. OR-k testing detects errors due to the selection of one or more extra product terms, and a conventional two-rail parity check on the outputs detects the other errors from single stuck-at, bridging, cross-point and broken line faults. The output patterns of an OR-k testable PLA must be unordered. For such PLAs, certain subsets of the outputs take on an all 1's pattern only in the presence of an extra product term error condition. A limited concurrency PLA tested by OR-k testability is strongly fault secure.

Design of fault-diagnosable and repairable folded PLAs for yield enhancement

A defect-tolerant PLA (programmable logic array) design with a simple column folding technique to enhance the probe yield is presented. The results show that the design requires less die size than a previous design, while still achieving full diagnosability of single and multiple stuck-at, bridging, and crosspoint faults. The design concept is readily extended to other folding techniques. Among the various folding techniques, the trade-offs are the density improvement and regularity, i.e. the density improvement is often paid for as higher irregularity. In fact, the irregularity often results in a higher defect density. It is concluded that a density improvement does not guarantee a higher overall yield.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A fault model for PLAs

A fault model for programmable logic arrays (PLAs) is discussed. This model maps realistic failures on four classes of faults: multiple stuck-at faults, multiple bridging faults, multiple crosspoint faults, and faults due to breaks in lines. It is shown that multiple stuck-at faults are equivalent to multiple crosspoint faults, multiple bridging faults are sub-equivalent to multiple crosspoint faults, and the set of patterns detecting multiple crosspoint faults is a subset of the set of patterns detecting multiple bridging faults. Hence, the set of patterns detecting multiple crosspoint faults also detects all multiple stuck-at faults and multiple bridging faults. This reduces the fault model for PLAs to two classes: multiple missing/extra crosspoint faults and multiple breaks.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Function dependent fully testable programmable logic array

Two techniques for designing function-dependent easily testable programmable logic arrays are presented. The techniques can detect all the multiple stuck-at, crosspoint and bridging faults, as compared with most of the existing techniques where some of the faults, especially bridging faults, remain undetected.

Universal built-in self-test procedure for CMOS PLA's

The authors present a built-in self-test (BIST) programmable logic array (PLA) design in CMOS technology that provides a high percentage of coverage for multiple stuck-at, crosspoint, and bridging faults and, furthermore detects all simple stuck-open faults in the AND and OR planes and all multiple stuck-open faults in the AND plane. As the test patterns used are the same for all PLAs, a universal test for PLAs is defined. The hardware overhead complexity for this scheme resembles that of previous proposals, although the number of different test patterns used has been reduced. >

Design and testing of easily testable PLA

A technique for designing and testing of an easily testable programmable logic array (PLA) is proposed in which the test vectors are derivable directly from the personality matrix of the PLA by simple algorithms. This technique requires few test vectors for testing. The test evaluation is simple, because in the fault-free condition, the output patterns for some of the test vectors are the same as those in the personality matrix of the PLA and are all 0s for the rest of the test vectors. The PLA is augmented with an extra shift register. It has negligible, if any, effect on the speed of the PLA in normal mode of operation as no extra hardware is added to the input output paths. High fault coverage is obtained in the proposed technique. All single and multiple stuck-at faults, all single and multiple crosspoint faults, and most of the bridging faults and their combinations are detected. The testing technique, however, is function dependent.

Easily testable PLA-based finite state machines

An outline is presented of a synthesis procedure that, beginning from a state transition graph (STG) description of a sequential machine, produces an optimized easily testable programmable logic array (PLA) based logic implementation. Previous approaches to synthesizing easily testable sequential machines have concentrated on the stuck-at-fault model; for PLAs, an extended fault model called the crosspoint fault model has been used. The authors propose a procedure of constrained state assignment and logic optimization which guarantees testability for all combinationally irredundant crosspoint faults in a PLA-based finite-state machine. No direct access to the flip-flops is required. The test sequences to detect these faults can be obtained using combinational test generation techniques alone. This procedure thus represents an alternative to a scan design methodology. Results are presented which show that the area/performance penalties in return for easy testability are small.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A Function Dependent Concurrent Testing Technique for PLAs

An algorithm is proposed for generating function dependent test vectors for NOR-NOR PLAs, which can test one or more crosspoint (cp) faults simulataneously in addition to other faults by sensitizing one or more product lines at a time. This technique reduces the number of test vectors by a substantial amount. The conditions for simultaneous testing of product terms are also found out. The generated vectors test all single and multiple stuck-at and cp faults and most of the bridging faults. A technique has been developed for the generation of the vectors with increased probability of detection of bridging faults.

On the design of high-yield reconfigurable PLA's

An approach to the design of reconfigurable programmable logic arrays (RPLAs) is proposed in which diagnosis of faults and reconfiguration are performed simultaneously. The approach also takes advantage of a laser programmable interconnect to simplify the test circuitry and area overhead. The RPLA design presented makes it possible to diagnose and repair faults on bit lines, product lines, and output lines. The unrepairable area in the RPLA is kept to a minimum. Only one extra input is required for testability. A mapping process for masking out missing crosspoint faults is employed to further enhance the yield of PLAs. Experimental results on the area overhead and the yield of the proposed RPLAs are presented. The field of the proposed RPLAs is higher than that of the original PLAs. >

Switch-level testability of the dynamic CMOS PLA

Functional testing, as opposed to parametric testing, plays an important role in testing VLSI integrated circuits. However, it appears that designs are not always carefully analysed in advance to determine precisely which faults are clean, i.e. testable by logic means alone. The programmable logic array (PLA) is a popular circuit form used to implement a system of Boolean functions over a set of input variables. This paper considers the testability of the dynamic CMOS PLA with respect to an extended switch-level fault model that includes node faults, transistor stuck-opens and stuck-ons, interconnect breaks, ohmic shorts, and crosspoint faults. Single occurrences of each fault in the fault model are classified as either clean, unclean, or clean subject to conditions on the products and output functions computed by the PLA. Finally, a modified dynamic CMOS PLA design is described and its improved switch-level testability properties are given.

Reprogrammable FPLA with universal test set

A field programmable logic array is presented which can be programmed. This FPLA uses one-transistor reprogrammable switches instead of fuses. The FPLA design presented here is also easily testable. In this design, the PLA is partitioned into two parts, which are tested independently. The delay is kept to a minimum for each test vector. Furthermore, parallelism is employed during testing, and thus minimal test time is obtained. It employs a universal test set of minimal length to detect all single crosspoint faults, stuck faults and bridging faults. This universal test set also covers the majority of multiple faults. The test set is simple and avoids test generation complexity. A user can reprogram and test the proposed PLA.