Abstract
A new hardware scheme for easily testable PLA-based finite state-machines is proposed. With this scheme, all combinationally nonredundant crosspoint faults in the PLA logic implementation are testable. Moreover, test generation is easily accomplished because short systematic initialisation sequences exist for each internal state in the machine and unit length distinguishing sequences, which hold under the faulty condition existing for every true faulty state pair. The authors present an outline of the proposed scheme, which consists basically of the addition of some state transitions and their output to the state transition graph (STG) of the machine. A test generation procedure is described which requires neither fault simulation nor manipulation of the machine's STG.
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