Testable synthesis of synchronous sequential circuits considering strong-connectivity using undefined states

Abstract

In this paper, usage of undefined states on a state transition graph (STG) is addressed to obtain high fault coverage, in the area of synthesis for testability (SFT) of synchronous sequential circuits. Basically, a given STG could be modified by adding undefined states and distinguishable transitions so that each state might be included in one strongly-connected component as much as possible. Such modification has an effect on decreasing the number of redundant faults because redundant faults caused by the existence of unreachable states on an STG may be eliminated. For the modification, we propose two algorithms for both incompletely specified STGs and completely specified STGs, respectively. In the case of incompletely specified STGs, undefined states are added using unspecified transitions of defined states. In the case of completely specified STGs, undefined states are added by changing transitions specified on an STG while preserving state equivalence. Experimental results with MCNC benchmarks show that the number of redundant faults of gate-level circuits synthesized by our modified STGs are reduced, resulting in high fault coverage as well as short test generation time.