Critical Dimension Variation Research Articles

Controlling gate-CD uniformity by means of a CD prediction model and wafer-temperature distribution control

A technique for predicting wafer temperature was developed, and a model for predicting critical dimension (CD) was devised. Using this technique and model in combination makes it possible to calculate wafer temperature during gate etching within an accuracy of 1 °C and to predict CD distribution after plasma etching. Etching at a temperature for uniform CD given by the CD prediction model reduces the CD variation (3σ) during gate etching from 2.3 to 1.5 nm. Applying this temperature prediction technique and CD prediction model together will contribute to improving etching apparatus design and process development.

Predicted effect of shot noise on contact hole dimension in e-beam lithography

The requirements on dimensional control of contact holes scale with the technology node and are reaching values of only a few nanometers. The allowed 3σ variation of the diameter is typically 10%. In traditional optical lithography, cross section variations occur mainly on a global scale as a result of slowly varying image or process parameters. For electron beam lithography and extreme ultraviolet (EUV) lithography, local variations need more attention. The authors have developed a model for the critical dimension (CD) variations resulting from shot noise and checked the results with Monte Carlo simulations. The model predicts that the necessary number of particles to write a contact is independent of the contact diameter, when both the requirements, the resolution, and resist’s acid diffusion length scale with the size of the contacts. The minimum number of particles required under ideal circumstances is about 500 per contact, but under more realistic circumstances, e.g., for electron beam lithography at low voltages, a typical number of electrons per contact is 3900. This means that contact holes at the “32nm node” (45nm diameter at 90nm pitch with 3σ of 4.5nm) require a dose of about 30μC∕cm2 and at the “22nm node” about 60μC∕cm2. If the molecular size of the resist molecules contributes to a size variance, or if high energy electrons or EUV photons are used, the required dose may be substantially higher.

Dependence of power trench metal-oxide-semiconductor field-effect transistor processes on wafer thickness

The dependence of trench metal-oxide-semiconductor field-effect transistor processes on wafer thickness has been studied. In the photolithography process, it was found that the photoresist thickness decreased with the decrease of wafer thicknesses. This is due to the fact that thinner wafer has less thermal mass and hence less dissipation time. Unless compensated for, this change in resist thickness adds to critical dimension and trench depth variations. After the rapid thermal processing, the thinner wafers exhibited a lower resistivity and higher silicide stress (i.e., 3.23E+10dyn∕cm2 for 508μm wafers and 4.60E+09dyn∕cm2 for 675μm wafers). Also, the stress is more uniform across the thinner wafers, possibly due to uniform Si-rich TixSiy (x<y) phase. Both Z-contrast transmission electron microscopy imaging and energy dispersive x-ray profiling on the silicide layers of the thicker wafers revealed a Ti-rich layer (possibly TiSi) on the top of TixSiy (x<y) layer and at the Si-silicide interface; whereas only scattered regions of Ti-enriched regions were observed in thinner wafers. Higher temperature in thinner wafers seems to assist in the removal of this Ti-rich layer.

Explicit expression on specifications of mask mean to target and mask uniformity

An analytic expression on the relationship of the mask mean to target (MTT) and the mask uniformity specifications is suggested. The MTT and uniformity (M-U) curve defines the boundary of the specification region, and this curve is explicitly expressed as mask error enhancement factors (MEEFs), dose sensitivities, and critical dimension (CD) tolerances of cell and peripheral patterns. This curve shows linear relationships between mask M-U. The decrease of the mask uniformity allows the increase of the mask MTT margin. M-U specifications are suggested for 63, 73, and 90nm design rules. In this experiment, the tolerance of the cell pattern is given as the product of the MEEF and the mask uniformity margin which is specified as 60% of the total CD variation at the given design rule, while that of the peripheral pattern is set to be 10% of the design rule. An isolated pattern is selected as a peripheral pattern because its pitch size is infinite. The mask MTT specification for 63nm is ±2.3nm at the mask uniformity of 2.23nm. For 73nm design rule, specifications of mask MTT are ±1.94 and ±1.48nm at the mask uniformities of 2.32 and 3.31nm at the process constants (k1’s) of 0.295 and 0.322, respectively. For 90nm design rule, the mask MTT specifications are ±3.89 and ±4.13nm at mask uniformities of 3.89 and 4.13nm for k1’s of 0.364 and 0.396, respectively.

Effect of critical dimension variation on SAW correlator energy

The effect of critical dimension (CD) variation and metallization ratio on the efficiency of energy conversion of a surface acoustic wave (SAW) correlator is examined. We find that a 10% variation in the width of finger electrodes predicts only a 1% decrease in the efficiency of energy conversion. Furthermore, our model predicts that a metallization ratio of 0.74 represents an optimum value for energy extraction from the SAW by the interdigitated transducer (IDT).

Correction of stray-light-induced proximity effect by complementary double exposure in microlithography

Stray light (flare) in optical microlithography causes critical dimension (CD) variation. We present a method to correct the CD variation by equalization of the stray-light distribution. This is achieved by doing a second “correction” exposure with the mask that has the reverse tone compared to the mask of the first exposure. A small exposure dose and large defocus are required for the correction exposure to mimic stray light. This correction method has been confirmed by experiments for 100nm features with standard ArF (193nm) lithographic processes.

Impact of stray light depending on image quality: An approximation using total integrated scatter

Stray light (or flare) in optical microlithography causes critical dimension (CD) variation depending on local mask transmission. This CD change can be approximately estimated using image quality and total integrated scatter (TIS) which is defined as the integral of stray-light characteristic function, power spectral density. This TIS approximation is experimentally verified for various features on ArF lithographic processes and is particularly useful for determination of tool specification for a given application.

Improving critical dimension accuracy and throughput by subfield scheduling in electron beam mask writing

Resist heating in high-voltage, high-throughput electron beam (e-beam) mask write is a significant source of critical dimension (CD) distortion. Excessive heating on the reticle determines changes in resist sensitivity, which in turn cause significant CD variation. CD distortions on the reticle are replicated onto the wafer with increased magnitude as determined by the mask error enhancement factor (MEEF). As designs enter the sub-90nm regime, CD variation has a significant impact on performance, performance variation, and product yield. Previous methods for reducing CD distortion include usage of lower e-beam current density, increased delays between electron flashes, and multipass writing. However, all of these methods lower mask writing throughput, which is increasingly becoming a limiting factor in semiconductor industry productivity. In this paper, we propose a novel method for minimizing CD distortion and maximizing mask writing throughput. By scheduling the writing of subfields, we perform simultaneous optimization of mask writing order and e-beam current density. We perform subfield scheduling by evaluating resist temperature of subfield orderings using a fast analytical temperature model. Simulation experiments show that the new subfield scheduling method can reduce the maximum resist temperature up to 12°C over existing sequential writing methods with unchanged mask writing throughput. Alternatively, improved subfield scheduling can enable the use of higher beam current densities, leading to increased writing throughput without compromising CD control.

Understanding the impact of source displacement error on sub-90nm patterns using a fresnel zone plate

Illumination source radiance distribution has a significant impact on vertical-horizontal bias and critical dimension (CD) variation on production wafers. In this article, the impact of source displacement error (SDE) on sub-90nm patterning is studied. A Fresnel zone plate (FZP) is adopted as a metrology to quantify the amount of SDE. Experimental data show that some of pupil-fills may have more than 50mrad of SDE and it could cause a serious pattern shift and/or CD asymmetry. A detailed description of FZP design specifications and application results are presented. Finally, SDE tolerance limits to print sub-90nm features are discussed.

Local critical dimension variation from shot-noise related line edge roughness

Shot noise effects are important to take into account both in the design of resists for lithography and in the design of lithography tools. The statistics of electron or photon arrival gives rise to dose variations, which translate to variations in the size of written features. It is possible to model the shot noise effects in an analytical equation, which shows the influence of all relevant parameters. The sequence of subsequent events in the resist: Secondary electron creation, acid generation, and acid diffusion are incorporated in the model. The model then allows the evaluation of the minimum resist sensitivity necessary for a certain required critical dimension control.

Thin-film optimization strategy in high numerical aperture optical lithography, part 2: applications to ArF

The methodology of the optimization of a thin-film stack for high-NA optical lithography is different from that of the conventional low-NA case, since there are many new factors that need to be considered simultaneously. These include polarization dependence of the reflection coefficient, impact from variation of the angle of incidence, low energy coupling efficiency at the air/resist interface for TE waves, and critical dimension (CD) variation resulting from the bulk effect. In this work, we show that in the extreme high-NA regime, it is hardly possible with existing materials to realize a perfect top antireflection coating that satisfies simultaneous requirements of minimizing the swing effect as well as maximizing throughput and image contrast. Fortunately, for immersion lithography, it is very probable to realize such a top antireflection coating, even when NA is close to the physical limit. We also show that the impact from variation of the angle of incidence can be overcome by implementing top/bottom antireflection coating optimized at low/high angles of incidence, or vice versa. We finally show that CD variation resulting from the bulk effect can be compensated in half a swing period by fine tuning the swing effect.

ArF Photoresist Parameter Optimization for Mask Error Enhancement Factor Reduction

The mask error enhancement factor (MEEF) is the best representative index for critical dimension (CD) variation in a wafer which is amplified by real specific mask CD variation. As already clarified in previous reports, MEEF is increased by reducing k1 (process ability index) or pattern pitch. The illumination system, just like lens aberration or stage defocus effects directly the MEEF value, but the leveling or species of a substrate and the resist performance are also strongly related to the MEEF value. In practice, when engineers set up the photoprocess for fabricating the miniaturized structures of current devices, they established minimum shot uniformity target such as the MEEF value within wafer uniformity and wafer-to-wafer uniformity, in addition to the usable depth of focus (UDOF) or exposure latitude (EL) margin. We examined MEEF reduction by checking the differences in resist parameters and attempted to correlate the results between experiment and simulation. Solid-C was used as the simulation tool. The target node is dense line/space pattern (L/S) of sub-80 nm and we used the same illumination conditions. We calculated MEEF values by comparing with the original mask uniformity using the optical parameters of each resist type. The normalized image log slope (NILS) showed us some points of the saturation value with pupil mesh points and the aberration is not considered. We used four different types of resist and changed resist optical properties (i.e., n, k refractive index; A, B, and C Dill exposure parameters). It is very difficult to measure the kinetic phenomenon, thus we chose the Fickian model in post exposure bake (PEB) and the Weiss model for development. In this paper, we suggest another direction of photoresist improvement by comparing the resist parameters with the MEEF values at different pitches.

Impact of Long-Period Line-Edge Roughness (LER) on Accuracy in Critical Dimension (CD) Measurement and New Guideline for CD Metrology

The influence of long-period line-edge roughness (LER) on measured critical dimension (CD) is identified, and a guideline is proposed for CD measurement which is free from LER impact. The width of a line pattern measured by critical dimension scanning electron microscope (CD-SEM) is a local CD, which deviates from the averaged CD due to long-period LER. This LER impact on the CD measurement is investigated in two typical measurements of CD-SEM, namely, the evaluation of across-wafer CD variation and the dynamic repeatability of the equipment. It is shown that both results strongly depend upon the height of the inspection area along the pattern edge (L) due to long-period LER. To obtain an accurate CD, this LER impact on variation in measured CD should be reduced sufficiently. It is found that a large L can reduce LER impact, and a 2-µm-high inspection area is recommended for CD measurement. Furthermore, the validity and limitation of the “patchwork method”, in which plural inspection areas are connected to obtain one large area, are examined.

Effect of a surface inhibition layer on line edge roughness

Line edge roughness (LER) is one of the most important issues in sub-100nm lithography. We have designed and implemented an experiment to study the coupled effect from acid depletion and percolation property of development process of Chemically Amplified Resist (CAR) on Line Edge Roughness (LER). The resist selected is UV-5 (a positive tone CAR from Shipley), known to be fairly sensitive to acid loss. After development, the resist is analyzed using high-resolution SEM (LEO 1550 VP), and an in-house made software is used for LER measurements. Our results indicate that the effect on LER and Critical Dimension (CD) variation depends on image modulation, and that aggressive lithography (low modulation image) will be more sensitive to the environment. In addition, it is shown that percolation development with stochastic energy deposition model can explain all the observed phenomena.

Process Characterization and Control of Polycrystalline SiGe as the Gate Electrode in CMOS Fabrication

Polycrystalline (poly-SiGe) films have been proposed as a promising alternative to the currently employed polycrystalline silicon (poly-Si) gate electrode for complementary metal-oxide-semiconductor (CMOS) field effect transistor technology due to lower resistivity, less boron penetration, and less gate depletion than that of poly-Si gate. The use of Poly-SiGe as the gate electrode, however, has serious implications on transistor fabrication processes such as plasma dry etching, resist ashing, wafer cleaning, and oxidation. In this work, we investigate the impact of these processes on the polycrystalline profile and the critical dimension (CD) of the gate electrode. The process improvements and an integration scheme using an oxide liner are presented to minimize the profile and CD variations introduced by the fabrication processes. © 2004 The Electrochemical Society. All rights reserved.

Optimum dose for shot noise limited CD uniformity in electron-beam lithography

To maximize the performance of an electron-beam lithography system the resist sensitivity must be chosen carefully. Very sensitive resists require only a low illumination dose, thus increasing the throughput. However, shot noise effects may give rise to unacceptable line edge roughness and variations in critical dimension (CD). In this study, the physical parameters which influence the effect of shot noise statistics on CD uniformity (CD-u) and linewidth roughness (LWR) are determined and an analytical model for CD-u and LWR is derived. It is found that the CD-u and LWR depend on the dose, the Gaussian beam probe size, the diffusion length dr of secondary electrons and acids in resist. The influence of background dose and non-shot-noise dose variations must also be taken into account. Monte Carlo simulations are performed to obtain the statistical variation of the two-dimensional solubility distribution of illuminated resist in a developer. The results of this simulation are used to validate the model. For the CD-u and the LWR, different expressions were found for describing the effect of the shot noise because, to describe the LWR, an extra factor must be incorporated to include the effect that spatial frequencies lower than 2 CDs do not have a contribution. Also, the area over which the dose must be integrated for the shot noise calculation is different for CD-u and LWR. For CD-u this area depends on dr∙CD, for LWR on dr2. From the model it can be concluded that shot noise has a significant effect on both the CD uniformity and the LWR and cannot be neglected in the optimization of the dose for high-throughput electron-beam lithography. With the specific relation between the current and the resolution of an e-beam tool, an expression for CD uniformity is found from which the throughput can be maximized for the required CD-u by optimizing the dose, probe size, and diffusion parameter. The background dose and the other dose variations are input parameters for such an optimization. For electron-beam systems with a typical resolution of 30nm and a required CD uniformity contribution of 3.5nm (3σ) due to all dose variations, a dose of 30μC∕cm2 is needed if 20% background and 3% (3σ) non-shot-noise dose variations are taken into account.

Electron-beam SAFIER™ process and its application for magnetic thin-film heads

We have coupled the SAFIER™ (shrink assist film for enhanced resolution) process with electron-beam lithography for the fabrication of the write top pole structures for thin-film heads. The SAFIER™ process is designed to physically shrink trench patterns and contact holes with very little deterioration of the resist profile. In this article, we will present the experimental results of the SAFIER™ process for the fabrication of the write top pole. We investigate the SAFIER™ process concerning several key processing issues, including shrink resolution capability, repetition of the SAFIER™ process, shrink-sensitive baking conditions, resist sidewall profile, and line edge roughness (LER) after shrinking of the trench. The experimental results show that this process not only shrinks the size of resist trenches and contact holes, but also improves LER and critical dimension variation. We demonstrate the capability of printing top pole structures with pole widths of sub-20nm in a 0.30-μm-thick resist (aspect ratio>15:1), and electroplated top pole structures of 50nm in a 0.50-μm-thick resist (aspect ratio=10:1).

Effects of flare in extreme ultraviolet lithography: Learning from the engineering test stand

One of the technical challenges for introducing extreme ultraviolet lithography (13.5 nm) into high volume manufacturing is flare. Flare reduces aerial image contrast and creates critical dimension (CD) variations across the die due to local chrome density dependent flare variations. Therefore, it is important to experimentally characterize flare on a full-field stepper and develop methods to mitigate and compensate for its effects. In this article, the impact of flare on depth of focus and exposure latitude are experimentally quantified using the engineering test stand. In addition, we report a marked increase in line width roughness due to high levels of flare in the optical system. A technique for the extraction of the point spread function due to scatter using density dependent CD data has been demonstrated for more accurate flare variation compensation.

Advanced Gate Etching for Accurate CD Control for 130-nm Node ASIC Manufacturing

This paper presents a methodology for gate trim etching to obtain accurate critical dimension (CD) control for 130-nm node ASIC manufacturing. In order to reduce mask-to-mask CD variation in gate trim etching, correlation between mask layout and amount of gate trim is investigated. It is found that trim rate strongly depends on gate peripheral length. A novel feed-forward technology to reduce both wafer-to-wafer variation and mask-to-mask variation is developed with the knowledge of peripheral length effect. This technology can also reduce CD variation within die and the CD bias between dense and isolated lines is compensated by optical proximity correction rules. This novel feed-forward technology is one solution for improving every gate CD variation: within die, within wafer, wafer-to-wafer, and mask-to-mask.

FPGA as Process Monitor—An Effective Method to Characterize Poly Gate CD Variation and Its Impact on Product Performance and Yield

This paper illustrates how field programmable gate array (FPGA) is used as a process monitor for yield and performance improvements. Poly gate critical dimension (CD) variation has been increasingly affecting product performance and yield in advanced process technology. Here, a built-in-self-test (BIST) pattern-based poly gate CD measurement (Tilo) methodology is introduced in FPGA product. The FPGA circuit is programmed into a small, local BIST pattern (Tilo) and its delay is accurately reflecting local poly gate CDs and variation. This methodology can conveniently capture poly gate CD statistical variation at both the intrafield and interfield level. This paper shows that the Tilo measurement is very useful in poly process debugging and yield improvement.