Abstract
This paper presents a methodology for gate trim etching to obtain accurate critical dimension (CD) control for 130-nm node ASIC manufacturing. In order to reduce mask-to-mask CD variation in gate trim etching, correlation between mask layout and amount of gate trim is investigated. It is found that trim rate strongly depends on gate peripheral length. A novel feed-forward technology to reduce both wafer-to-wafer variation and mask-to-mask variation is developed with the knowledge of peripheral length effect. This technology can also reduce CD variation within die and the CD bias between dense and isolated lines is compensated by optical proximity correction rules. This novel feed-forward technology is one solution for improving every gate CD variation: within die, within wafer, wafer-to-wafer, and mask-to-mask.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.