Simulation-based critical-area extraction and litho-friendly layout design for low-k 1 lithography

Abstract

As the lithography process approaches to the low k1 regime, the layout designers are forced to design the litho-friendly layout, which considers the process margin and mask error enhancement factor (MEEF). In addition, the lithography engineers are also impelled to optimize the optical proximity correction (OPC) rules at the full-chip level to eliminate the failures of the printed image on the wafer. Therefore, we have newly developed the simulation-based critical area extraction (CAE) and litho-friendly layout (LFL) design methodology based on the layout editor environment to design the litho-friendly layout and optimize the OPC rules. In this methodology, the critical areas of the full-chip level post-OPC layout, which have the lower process margin and larger critical dimension (CD) variation, are automatically extracted by evaluating the focus-exposure window, normalized image log-slope (NILS) and edge placement error (EPE). The extracted critical areas are sorted according to their causes of failures (i.e., notching, bridging, line-end shortening and larger CD variation, etc.). In order to maximize the process margin and minimize the MEEF at the full-chip level, layout designers and lithography engineers modify the original layout and optimize the OPC rules of the sorted critical areas based on the lithography simulator. The simulator uses the mask decomposition and selective simulation method to reduce the simulation time at the full-chip level. For the convenient CAE, process margin evaluation and layout optimization, the CAE function and lithography simulator are combined with the layout editor environment. Applying this methodology to the memory device of sub-90nm design rule, we have validated that our methodology can capture the pattern failures at the full-chip level and optimize both the original layout and OPC rules of those areas.