Solder Joint Crack Research Articles

Development of Wafer Level Package Platform for High Reliability Crossover MCUs

Fan in and fan out wafer level packages are primarily used in the industry for applications in handheld consumer electronic products. The key benefits of wafer level package (WLP) are small form factor, reduced cost, improved electrical and thermal performance. WLP investigated in this study are directly surface mounted on PCB and have no intermediate substrate. Direct mount of package on PCB, leads to significant CTE mismatch between the package and board which stresses the package solder joint, leading to cyclic fatigue induced solder joint cracking. To overcome the solder joint cracking, stiffer solder alloys have been evaluated. However, higher stiffness of the solder alloy shifts the cyclic stress induced failure, from the solder joint to the package metal interconnect layers. Moreover, WLP on advanced silicon node have fragile low-k and extremely low-k back end of line dielectric layers that also crack or delaminate in cyclic fatigue. In this work extensive WLP platform development has been done with following DOE variables; multi-layer package routing, dielectric materials, solder alloys, solder ball pitch and diameter. Developed packages passed and outperformed the following product reliability qualification conditions: high temperature storage life (150°C, 2000 hours), highly accelerated stress test (110°C / 85%RH / Bias, 528 hours), application level temperature cycling ((-40 °C to 125 °C, 600 cycles), board level temperature cycling (-40 °C to 125 °C, 500 cycles) and board level drop test (1500g/0.5ms, 30 drops). Excellent reliability, functional performance, and successful chip package integration was achieved for WLP for crossover MCU products.

Numerical investigation of thermal fatigue crack growth behavior in SAC305 BGA solder joints

PurposeThis study aims to investigate the reliability issues of microvoid cracks in solder joint packages exposed to thermal cycling fatigue.Design/methodology/approachThe specimens are subjected to JEDEC preconditioning level 1 (85 °C/85%RH/168 h) with five times reflow at 270°C. This is followed by thermal cycling from 0°C to 100°C, per IPC-7351B standards. The specimens' cross-sections are inspected for crack growth and propagation under backscattered scanning electronic microscopy. The decoupled thermomechanical simulation technique is applied to investigate the thermal fatigue behavior. The impacts of crack length on the stress and fatigue behavior of the package are investigated.FindingsCracks are initiated from the ball grid array corner of the solder joint, propagating through the transverse section of the solder ball. The crack growth increases continuously up to 0.25-mm crack length, then slows down afterward. The J-integral and stress intensity factor (SIF) values at the crack tip decrease with increased crack length. Before 0.15-mm crack length, J-integral and SIF reduce slightly with crack length and are comparatively higher, resulting in a rapid increase in crack mouth opening displacement (CMOD). Beyond 0.25-mm crack length, the values significantly decline, that there is not much possibility of crack growth, resulting in a negligible change in CMOD value. This explains the crack growth arrest obtained after 0.25-mm crack length.Practical implicationsThis work's contribution is expected to reduce the additional manufacturing cost and lead time incurred in investigating reliability issues in solder joints.Originality/valueThe work investigates crack propagation mechanisms of microvoid cracks in solder joints exposed to moisture and thermal fatigue, which is still limited in the literature. The parametric variation of the crack length on stress and fatigue characteristics of solder joints, which has never been conducted, is also studied.

Board-Level Reliability of Lead-Frame Based Substrate and Surface Finishing Technology

Lead-frames have been widely used in the semiconductor package assembly field, and QFN (Quad flat no leads) has the advantages of miniaturization and cost reduction of the semiconductor package. It has had limited use in automotive or defense products because of its board-level reliability. Nevertheless, due to the advantages of QFN packages, there is a trend toward using QFNs in automotive packaging. Automotive use would also require a wettable flank design of the QFN leads and automated optical inspection (AOI) of solder joints. New lead forming and surface finish technologies, including wettable flank design, are expected to improve reliability and enable AOI inspection, but much research is needed. This study investigated the board-level reliability of various QFN lead designs and surface finishes. All lead frames with different structures and surface finish types were assembled under the same conditions and then mounted on a daisy chain printed circuit board to evaluate board-level reliability. Accelerated thermal cycling (TC) tests were performed per IPC-9701A rev 2/2006 over a temperature range of -40°C to 125°C and 6080cycles. Lastly, each package type tested was cross-sectioned, and failure analysis was performed by observing the solder joint crack for all leg samples.

A failure location technology for SiP devices based on TDR nondestructive testing method

PurposeTraditional nondestructive failure localization techniques are increasingly difficult to meet the requirements of high density and integration of system in package (SIP) devices in terms of resolution and accuracy. Time domain reflection (TDR) is recognized as a novel positioning analysis technology gradually being used in the electronics industry because of the good compatibility, high accuracy and high efficiency. However, there are limited reports focus on the application of TDR technology to SiP devices.Design/methodology/approachIn this study, the authors used the TDR technique to locate the failure of SiP devices, and the results showed that the TDR technique can accurately locate the cracking of internal solder joints of SiP devices.FindingsThe measured transmission rate of electromagnetic wave signal was 9.56 × 107 m/s in the experimental SiP devices. In addition, the TDR technique successfully located the failure point, which was mainly caused by the cracking of the solder joint at the edge of the SiP device after 1,500 thermal cycles.Originality/valueTDR technology is creatively applied to SiP device failure location, and quantitative analysis is realized.

THERMAL-INDUCED DAMAGE ON SOLDER JOINTS OF HIGH-DENSITY ADJACENT BALL GRID ARRAY COMPONENTS DURING THE REWORK PROCESS

Correlation between adjacent ball grid array (BGA) components' temperature and thermal-induced damage to their solder joints on both the top and bottom printed circuit board assembly (PCBA) sides during the rework process is studied in this work. Total often adjacent BGA components from the rework area on the top (F - K) and bottom (A - E) PCBA side were observed. The dye and pull (D&P) test results, infrared thermography images, and temperature measurements were analyzed for solder joint crack induced by the thermal damage with precise temperature measurement on each adjacent BGA component. Scanning electron microscope (SEM) analysis complemented the post-D&P test solder joint crack observation. The D&P test results shows that 76 % or higher and solder joint separation locations at the copper pad on BGA occurred when the temperature of the adjacent components of the rework location exceeded 195 °C and 210 °C on the centre and corner of the component, respectively.

Machine learning aided modelling of thermomechanical fatigue of solder joints in electronic component assemblies

Printed board assemblies, i.e. components soldered on printed circuit boards (PCBs), are exposed to thermal cycles responsible for fatigue cracking of solder joints as a result of thermal expansion mismatch between the constituting elements. Advanced finite element simulations are performed using a traction–separation law to represent the cracking process and a temperature-dependent elasto-viscoplastic model for the joint response. Predictions are successfully assessed towards machine learning processed experimental data. In particular, the high sensitivity of thermal ageing reliability to geometric dimensions and solder joint thickness is properly captured. Additional parameters, related to the PCB substrate, are also studied, opening new avenues towards design optimization.

Cardinal and Ordinal Directions Approach in Investigating Arrayed Solder Joints Crack Propagation of Ball Grid Array Semiconductor Packages

An accelerated reliability testing via thermal cycling test (TCT) was used to test ball grid array (BGA) components’ reliability. Five variables were observed; control sample J and samples K, L, M, and N were BGA component samples that have been exposed to TCT between 500 and 1250 cycles with the TCT profile in the range of 0 °C–100 °C. The crack orientation of the individual solder joint was analyzed along with the propagation path pattern on the solder array of the BGA component pad by analyzing the dye and pull test results that were then mapped and analyzed using the cardinal and ordinal directions approach. This is to determine the crack propagation path direction in the solder array and track the potential of warpage on the BGA package as the TCT cycles progressed. A cross section was performed on sample M with the 3-D X-ray and scanning electron microscopy (SEM) analysis to observe the solder joints’ fracture lines and surface topographies. The results showed that individual solder joint crack orientation is correlated to the crack propagation location on the BGA package. The solder joint from northwest (NW), northeast (NE), southeast (SE), and southwest (SW) of the BGA package is prone to solder crack compared to the solder joint array in the middle. A solder grain structure coarsening occurred at the crack propagation due to the high cyclic strain from the TCT.

Effect of high-frequency PCB laminate on thermal cycling behavior of electronic packaging structures

PurposeAs the solution to improve fatigue life and mechanical reliability of packaging structure, the material selection in PCB stack-up and partitioning design on PCB to eliminate the electromagnetic interference by keeping all circuit functions separate are suggested to be optimized from the mechanical stress point of view.Design/methodology/approachThe present paper investigated the effect of RO4350B and RT5880 printed circuit board (PCB) laminates on fatigue life of the QFN (quad flat no-lead) packaging structure for high-frequency applications. During accelerated thermal cycling between −50 °C and 100 °C, the mismatched coefficients of thermal expansion (CTE) between packaging and PCB materials, initial PCB warping deformation and locally concentrated stress states significantly affected the fatigue life of the packaging structure. The intermetallics layer and mechanical strength of solder joints were examined to ensure the satisfactorily soldering quality prior to the thermal cycling process. The failure mechanism was investigated by the metallographic observations using a scanning electron microscope.FindingsTypical fatigue behavior was revealed by grain coarsening due to cyclic stress, while at critical locations of packaging structures, the crack propagations were confirmed to be accompanied with coarsened grains by dye penetration tests. It is confirmed that the cyclic stress induced fatigue deformation is dominant in the deformation history of both PCB laminates. Due to the greater CTE differences in the RT5880 PCB laminate with those of the packaging materials, the thermally induced strains among different layered materials were more mismatched and led to the initiation and propagation of fatigue cracks in solder joints subjected to more severe stress states.Originality/valueIn addition to the electrical insulation and thermal dissipation, electronic packaging structures play a key role in mechanical connections between IC chips and PCB.

Backplate-reinforced structures for enhancing solder joint reliability of server CPU assembly under thermal cycling

ABSTRACT To meet the requirement of the high I/O and fine-pitch interconnects, the conventional insertion-mount socket for central processing unit (CPU) has been changed to surface-mount one with ball grid array. The solder ball joint reliability of the socket used in the CPU assembly becomes very important. In this study, the socket's solder joint reliability of the backplate-reinforced CPU assembly and its related mechanics under mechanical and thermal loadings are investigated experimentally using strain gauge and shadow moiré, and numerically by a finite element method (FEM). The validated FEM results have suggested that maximum stress of solder balls increases almost linearly with decreasing the backplate thickness under mechanical loading during the CPU assembly, but is insensitive to the backplate thickness under thermal loading during the thermal cycling. It is also found that the residual (bending) strain on the PCB proportional to the maximum von Mises stresses of solder joints (or balls) can be used as a key parameter to correlate with the solder joint failures or cracks during the thermal cycling. Overall, experimental and FEM results in this study reveal that solder joint reliability in the CPU assembly during thermal cycling can be improved by adopting the thicker reinforced backplate.

Failure Analysis and Evaluation of Material Compatibility of Solder Paste

Solder paste is mainly used for welding of resistance, capacitance, integrated circuit (IC) and other electronic components in surface mounted technology (SMT) industry, and the performance of solder paste has a significant impact on the reliability of electronic components. In this paper, processing defects, failure cases and mechanism of electronic components caused by solder paste are analyzed systematically. Improper application of solder paste during welding can lead to numerous processing defects including poor wetting, tombstoning, bridging, solder joint crack, solder ball spattering, corrosion and so on. Finally, an evaluation method of material compatibility is described in this paper, which provides a reference for ensuring the quality of electronic process material and improving the reliability of SMT products.

Failure Analysis and Modeling of Solder Joints in BGA Packaged Electronic Chips

In this article, the random vibration test and finite-element simulation analysis of SAC305 solder joints in BGA packaged electronic chips were carried out. A failure model for BGA solder joints was established based on the life data. And vulnerable parts in electronic chips were analyzed. First, the random vibration test was conducted. Second, a lognormal distribution model of solder joints by means of the life data was established and analyzed based on the fracture mechanics theory. Finally, the finite-element simulation model of BGA packaged electronic chip was established and discussed. Failure characteristics of solder joints at different positions in electronic chips were compared and the failure mode of the solder joint was discussed using the simulation result and the observation result with scanning electron microscope (SEM). The results show that the life of each single solder joint in BGA packaged electronic chips follows a logarithmic normal distribution under the random vibration. Solder balls located at the four outermost corners of the chip are subjected to the greatest stress, which are the weakest parts in electronic chips. Cracks in solder joints are generated near the package side and emerged from the edge of the intermetallic compound (IMC) layer with the largest curvature.

Two-Phase η′ + η Region in Cu6Sn5 Intermetallic: Insight into the Order–Disorder Transition from Diffusion Couples

The ongoing electrification and miniaturization increase the quality demands on solder joints. A bottleneck for solder joint reliability can be the intermetallic Cu6Sn5 phase, which undergoes a phase transition, implying a volume change in a relevant temperature range. There are contradicting reports on the sign and magnitude of this volume change, which possibly implements stresses and cracks in solder joints. To clarify the characteristics of the phase transition, different samples were manufactured by applying industrial-like standards and isothermal heat treatments around the predicted phase transition temperature. Using x-ray diffraction, a coexistence of ordered η′ and disordered η was detected in samples treated at 438–445 K. The lattice parameters show that the volume of the disordered η phase is approximately 0.64–0.65% smaller than the one of the ordered η′ phase. A comparison with order–disorder transitions in structurally related phases shows that the volume change based on order–disorder transitions is normally of opposite sign and around 0.1–0.2%. Therefore, an effect of different compositions is considered responsible for the volume change. Adopting the exact composition Cu6Sn5 (Cu1.20Sn) for the η′ phase, it was estimated, based on density functional theory calculations from the literature, that the coexisting η phase assumes lower Cu content of Cu1.171Sn at 438 K and Cu1.174Sn at 445 K. In contrast, the lattice parameters of η′, generated at different temperatures, imply a largely temperature-independent composition of Cu1.20Sn. This leads to adjustments of the Cu-Sn phase diagram.

Developing a Machine Vision Inspection System for Electronics Failure Analysis

Ball grid array (BGA) package components are widely used in various electronic products, as they shorten the conductive path and greatly reduce the interference during current transmission. The BGA component solder ball has little flexibility for distortion, which may cause stress concentration and solder joint cracking. Red ink dye stain analysis testing can visually analyze the cracking area and the interface of the solder joint. At present, most companies use failure analysis (FA) specialists to observe the components and circuit board end images with a microscope. As component packaging technology becomes more complex and the number of input–output (I/O) signals of the chip increases sharply, FA operations require a long time and may be misjudged due to personnel fatigue and subjective determination. This paper aims to develop a machine vision image recognition system for intelligent decision analysis to judge the severity of solder ball cracking and the cracking interface type. This system uses charge-coupled devices (CCDs) to obtain the image. First, this paper uses affine transformation compensation to perform horizontal correction, which recognizes the actual position coordinates of each solder joint, estimates the solder ball according to the Hough Circle to obtain the center and the radius of the solder ball, and then a 2-D vector map (Gerber) file is used to establish the mask, and the region of interest (ROI) in the image feature is obtained through the iterator of the pixel access program. Second, the color space is converted from red, green, and blue (RGB) to hue, saturation, and value (HSV) to reduce the effects of light variations during image capture. This paper develops the range analysis model (uses the multiple-threshold method to judge whether a particular pixel in an image has the cracking (color) feature, as well as its cracking interface), and uses a morphology filter to filter image noise (filter pixels of overlapping features). The verification results show that the system developed in this paper and FA specialists have a consistency of more than 85% in the judgment of the severity of the cracking, and the false alarm ratio and the escape ratio of the system are about 9% and 16%, respectively. Regarding the judgment result of the solder ball cracking interface type, the consistency reaches 98%, which shows that the automatic failure identification system for solder joints, as developed in this paper, can effectively assist red ink solder joint FA.

Research on life evaluation method of solder joint based on eddy current pulse thermography.

With the wide usage of electronic packaging technologies such as Ball Grid Array in electronic industry, it is necessary to maintain its quality in order to meet the demand of electronic products for function, integration, and size reduction. However, as the size of solder joints in such technology decreases, the solder joints are more and more prone to defects. To solve the life prediction problem of small-size packages having interconnections in the high-density chip, a method based on the eddy current pulsed thermography (ECPT) is put forward to study the remaining life prediction of solder joints. A 3D induction heating finite element model is established, by which the crack length of defect solder joints can be distinguished using temperature field. At the same time, the remaining life of defect solder joints can be characterized by the length of the crack. Furthermore, the experiments are carried out on solder joints whose diameter is 0.4 mm. Both simulation and experiment results verify that it is reliable and convenient to use 3D induction heating based temperature field from ECPT to evaluate the remaining life of cracks in solder joints.

Methodology for Solder-Joint Lifetime Prediction of LED-Based PCB Assemblies

A solder-joint crack due to thermal fatigue affects the reliability of light emitting diode assemblies. A new methodology is presented for the solder-joint lifetime estimation under a wide range of working conditions. The proposed method is based on the combination of reliability design of experiments, computer aided structural analysis validated by thermal-cycling experiments, and surface response modeling.

Mechanism of Solder Joint Cracks in Anisotropic Conductive Films Bonding and Solutions: Delaying Hot-Bar Lift-Up Time and Adding Silica Fillers

Micron sizes solder metallurgical joints have been applied in a thin film application of anisotropic conductive film and benefited three general advantages, such as lower joint resistance, higher power handling capability, and reliability, when compared with pressure based contact of metal conductor balls. Recently, flex-on-board interconnection has become more and more popular for mobile electronic applications. However, crack formation of the solder joint crack was occurred at low temperature curable acrylic polymer resins after bonding processes. In this study, the mechanism of SnBi58 solder joint crack at low temperature curable acrylic adhesive was investigated. In addition, SnBi58 solder joint cracks can be significantly removed by increasing the storage modulus of adhesives instead of coefficient of thermal expansion. The first approach of reducing the amount of polymer rebound can be achieved by using an ultrasonic bonding method to maintain a bonding pressure on the SnBi58 solder joints cooling to room temperature. The second approach is to increase storage modulus of adhesives by adding silica filler into acrylic polymer resins to prevent the solder joint from cracking. Finally, excellent acrylic based SnBi58 solder joints reliability were obtained after 1000 cycles thermal cycling test.

Location resolved transient thermal analysis to investigate crack growth in solder joints

Solder joint cracking is a common failure mechanism in microelectronic packages. To investigate interconnect integrity and reliability different inspections are established with their strengths and weaknesses: X-ray, scanning acoustic microscopy (SAM), Infrared (IR)-Thermal Imaging as well as Transient Thermal Analysis (TTA). TTA is well suited to detect changes in the thermal path, i.e. delamination in a package. However, spatial resolution in plane of an interconnection is restricted. Still, spatial resolution is necessary to analysis the crack growth in solder joints. In addition the local temperature strongly depends on the local position of a bad thermal contact. In the paper an innovative new test method, location resolved transient thermal analysis (LrTTA), is developed and its potential is investigated. LrTTA is based on transient thermal measurement (TTM). It uses several distinct diodes on a test chip to detect the thermal performance of interfaces and assemblies. The temperature is measured by the forward voltage as a function of time at different locations on the chip. Spatial resolution is obtained, e.g. cracks, voids and thickness variations can be resolved in the interface. For first experimental application of the method, a silicon thermal test chip with four differently located diodes was employed. The test chip was soldered onto an Aluminium Insulated Metal Substrate (Al-IMS) and exposed to temperature cycles. TTM were performed directly after assembly and after specific temperature shock cycle numbers (−40°C/+125°C). After data processing, the increase of the thermal impedance of each diode between the initial “0” cycles and “n” cycles was obtained. The thermal data are correlated with void formation detected by X-ray. Crack or delamination is in addition detected with scanning acoustic microscopy (SAM). As a quantitative analysis, a finite element (FE) model was set up and applied to analyze the solder joint with and without voids and also the crack propagation in the solder joint during temperature shock testing. Based on the FE modelling, the thermal influence of voids can be calculated and thus these voids can be detected. Further, based on the numerical analysis, crack size and location can be identified.

Thermal cycling effect on the drop reliability of BGA lead-free solder joints

PurposeThe purpose of this paper is to study the drop reliability of ball-grid array (BGA) solder joints affected by thermal cycling.Design/methodology/approachThe drop test was made with the two kinds of chip samples with the thermal cycling or not. Then, the dyeing process was taken by these samples. Finally, through observing the metallographic analysis results, the conclusions could be found.FindingsIt is observed that the solder joint cracks which were only subjected to drop loads without thermal cycling appeared near the BGA package pads. The solder joint cracks which were subjected to drop loads with thermal cycling appear near the printed circuit board pads.Originality/valueThis paper obtains the solder joint cracks picture with drop test under the thermal cycling.

Modeling of intergranular thermal fatigue cracking of a lead-free solder joint in a power electronic module

Fatigue of lead-free solder joints remains the most critical concern in thermo-mechanical reliability of high power modules. Due to size miniaturization requirements, fatigue properties become strongly affected by features of the solder joint microstructure. Phenomenological fatigue models based on effective material properties at macro-scale only grossly predict the engineering lifetime for some specific boundary conditions while ignoring the important effects of the microstructural mechanisms of deformation. In this study, a 3D microstructure-informed model for reproducing the intergranular fatigue crack in the solder joint of a power module is developed. The submodeling technique is applied in order to investigate accurately the critical zone of the solder joint with reasonably reduced computational time. In the submodel, the anisotropic elasticity and crystal plasticity constitutive laws are integrated for the bulk grain material, while the decohesion at grain boundaries is modeled by the cohesive zone approach. The needed crystal plasticity parameters are calibrated using the Berveiller–Zaoui transition rule to fit tensile test data for the so-called InnoLot solder alloy, and physically-based concepts are used to estimate the cohesive zone parameters at the grain scale. Simulations demonstrate how fatigue cracking occurs and propagates at grain boundaries in the solder joint. A criterion is then presented to estimate the fatigue lifetime of the entire solder joint, based on specific quantities predicted numerically.

Reliability of SAC 105 and SAC1205N under Drop Tests

Abstract In this paper, the solder joint failure and the solder joint fatigue life in the Thin-profile Fine-pitch Ball Grid Array (TFBGA) Package was investigated by performing the drop test, and implementing a simulation model. Owing to the need to meet the increasing demands for functionality, microelectronic package reliability can be compromised and has become the key issue when executing drop tests. During impact in drop test, the deformation of PCB due to bending and mechanical shocks can cause solder joint crack. While this is a well-known issue, observing the solder joint responses during the test execution can be a challenge. Therefore, in this work, a simulation model approach has been developed to investigate the stress and strain of the solder joint during the drop test. In this research, the JEDEC Condition B drop test was simulated, characterized by 1500G peak acceleration and 0.5 ms duration. The drop test simulation model was successful in predicting the solder joint fatigue life with different solder joint materials, such as SAC105 and SAC1205N, while also facilitating result comparison to identify the most optimal structure.