Coupled Interconnects Research Articles

Analysis of the Impacts of Signal Slew and Skew on the Behavior of Coupled RLC Interconnects for Different Switching Patterns

This paper presents an in-depth analysis of signal slew and skew variations in coupled inductive lines for different switching patterns. It is revealed that variations of rise/fall time and skew alter the behavior of coupled inductive lines under different switching patterns. We observe that crosstalk noise reduces with increasing signal skew, and the impact of skew variation on crosstalk noise is more prominent for lines with strong capacitive coupling. A performance comparison is done between power supply and ground line as inductive shield, and it is found that ground lines work better than power lines in inductive crosstalk minimization. The 100%-delay measurement technique has been proposed as opposed to the conventional 50%-delay method, and we notice that the 50%-delay technique underestimates the propagation delay for an inductive dominant line with varying signal slew times. Closed-form equations for propagation delay in terms of signal slew time have been derived, which are within 9% of HSPICE-simulated results for a set of interconnect structures. These expressions are simple, and accuracy increases with growing number of interconnect lines.

Layer-to-layer optical interconnect coupling by soft-lithographic stamping

We designed and developed a fabrication method for a polymeric waveguide connecting multiple optical interconnect layers in three-dimensional integrated electro-optical systems, using a series of silicone elastomer stamps. The scalable process is a deterministic printing method, generating optical S-shaped polymeric lightwave coupling for interconnects among separate layers. General characteristics of S-shaped coupling among layers with various separation distances were investigated too. The soft-lithography fabrication process of this coupling interconnection design allows for significant advantages over traditional designs and fabrication methods in terms of insertion loss as well as 3D integration capability, when used in high-bandwidth printed circuit boards.

A novel interconnect crosstalk RLC analytic model based on the nanometer CMOS technology

Based on the nanometer CMOS technology, a novel parallel RLC coupling interconnect analytic model is presented. Based on the function approach and reduced order techniques, an analyzable expression for the outlying terminal of the disturbed line is derived by the model in the off-angle step input signal. In the 90 nm and 65 nm CMOS process, the proposed RLC coupling interconnect analytic model enables to estimate the crosstalk voltage within 4% errors compared with Hspice simulation for various interconnect coupling size. The proposed analytic model can be applied to the design of nanometer SOC and optimizing the design for VLSIs.

Proximity Coupled Interconnect Using Broadside Coupled Composite Right/Left-Handed Transmission Line

In this paper, the feasibility of composite right/left-handed transmission lines for realizing proximity coupled interconnects is reported. The proposed interconnects' resonant length can be miniaturized due to the zeroth order resonance supported by a composite right/left-handed transmission line resonator. In addition, the proposed interconnects can achieve broadside coupling because the zeroth order resonance occurs in the fast-wave region. Simulated and measured electric field distributions are shown to explain the broadside coupling phenomenon. To validate the arbitrary size and broadside coupling of the proposed interconnects, simulated and measured transmission characteristics are presented. The results show that low insertion loss can be achieved by using single and double broadside coupling between interconnects.

Waveform Relaxation Techniques for Simulation of Coupled Interconnects With Frequency-Dependent Parameters

The large number of coupled lines in an interconnect structure is a serious limiting factor in simulating high-speed circuits. Waveform relaxation based on transverse partitioning has been previously presented to address this problem for interconnects with constant per-unit-length parameters. This paper extends the waveform relaxation technique to handle the more difficult and important case of frequency-dependent parameters. The computational cost of the proposed algorithm grows linearly with the number of coupled lines

Fully Integrated AC Coupled Interconnect Using Buried Bumps

Presented is the complete demonstration of an assembled system using AC coupled interconnect (ACCI) and buried solder bumps. In this system, noncontacting input/output (I/O) are created by using half-capacitor plates on both a chip and a substrate, while buried solder bumps are used to provide power/ground distribution and physical alignment of the coupling plates. ACCI using buried bumps is a technology that provides a manufacturable solution for noncontacting I/O signaling by integrating high-density, low inductance power/ground distribution with high-density, high-speed I/O. The demonstration system shows two channels operating simultaneously at 2.5 Gb/s/channel with a bit error rate less than 10-12, across 5.6 cm of transmission line on a multichip module (MCM). Simple transceiver circuits were designed and fabricated in a 0.35 -mum complementary metal-oxide-semiconductor (CMOS) technology, and for PRBS-127 data at 2.5 Gb/s transmit and receive circuits consumed 10.3 mW and 15.0 mW, respectively. This work illustrates the increasing importance of chip and package co-design for high-performance systems.

Global adaptive synchronization of complex networks with nonlinear delay coupling interconnections

This Letter is dealt with global synchronization problem of a class of complex network systems with the time delay nonlinear coupling via adaptive methodology. The nonlinear functions and the delay coupling interconnections considered here are in a high-order polynomial form, which is less restrictive than the cases addressed in the literature. An adaptive controller is presented and it is shown by the Lyapunov method that the resulting synchronization error of the adaptive system is asymptotically stable. A numerical example is given to illustrate the effectiveness of the proposed controller.

Sensitivity Analysis of Coupled Interconnects for RFIC Applications

This paper investigates the sensitivity of on-wafer coupled interconnects to the Si CMOS process parameters. Experiments are conducted to emulate state-of-the-art and future technologies. Some important parameters characterizing the coupled interconnects have been examined. The influence of the process parameters on transmission, reflection, near-end, and far-end crosstalk capacities of the coupled interconnects are discussed

Simulation of Coupled Interconnects Using Waveform Relaxation and Transverse Partitioning

The large number of coupled lines in an interconnect structure is a serious limiting factor in simulating high-speed circuits. A new method is presented for efficient simulation of large interconnects based on transverse partitioning and waveform relaxation techniques. The computational cost of the proposed algorithm grows linearly with the number of coupled lines. In addition, the algorithm is highly suitable for parallel implementation leading to further significant reduction in the computational complexity.

Leaky mode directional coupler for prism coupling interconnection

A leaky mode directional coupler was fabricated with its beam shaped into a Gaussian-like profile and was experimentally demonstrated for suppressing the diffraction of an out-coupled beam. The demonstrated coupler consists of a multilayered waveguide with six layers that are embedded in a symmetric slab waveguide. The out-coupled beam profile was measured to be shaped into a Gaussian function by using the prism coupling method. There was an excellent agreement between the measured and theoretically predicted coupling angles, and it was also confirmed that the diffraction was suppressed.

Interconnect Coupling-Aware Driver Modeling in Static Noise Analysis for Nanometer Circuits

With geometries shrinking in nanometer technologies, crosstalk noise becomes a critical issue. Modern designs like system-on-chips have millions of noise-prone nodes, mandating fast yet accurate crosstalk noise analysis techniques. Using linear circuit model, static noise analysis can efficiently estimate crosstalk noise. Traditionally in static noise analysis, drivers' holding resistances are precharacterized without considering the potential impact of crosstalk noise. However, crosstalk induced voltage fluctuation strongly affects the behavior of nonlinear drivers. When facing different coupling interconnects and hence crosstalk noise, a driver's holding resistance can change dramatically. In nanometer circuits, this substantial variation of nonlinear drivers cannot be totally ignored. To achieve high-quality in noise estimation yet maintain the efficiency of linear circuit model, we propose a novel interconnect coupling-aware driver modeling method. Based on layout-extracted interconnect parameters and precharacterized driver models, an effective holding resistance is calculated to capture the impact of the nonlinear driver. Multiple aggressors with synchronous and asynchronous switching activities are also considered. The proposed method is simple, efficient, and enables on-the-fly calculation of the effective holding resistance. Experiments show that with negligible computation overhead, the coupling-aware driver modeling methodology can significantly improve the quality of static noise analysis.

A Statistical Approach to Derive an Electrical Port Model of Capacitively Coupled Interconnects

This paper considers the derivation of an electrical model at the input/output ports of a generic system of nonparallel interconnects that can be employed to simulate cross talk and delay effects through a conventional SPICE-like simulator. Only capacitive coupling effects are considered. The equivalent model of the interconnects system is determined through an iterative procedure based on the contemporary adoption of the floating random walk method that estimates the grounding and coupling capacitances per unit length and the Picard-Carson procedure that determines the entries of the transmission-matrix (T-matrix) representation at the electrical ports. It is shown that the entries of the T matrix can be efficiently computed through Monte Carlo integration.

A Novel Time-Domain Algorithm for Synthesizing Broadband Macromodels of Coupled Interconnects

Based on a novel multidimensional deconvolution algorithm (MDA), this paper proposes a time-domain approach to synthesize the broadband SPICE-compatible macromodels of coupled interconnects. The multiple conductor interconnects are excited either experimentally by TDR or numerically by the step-like source in finite difference time domain (FDTD) method. According to the time-domain scattered data, the macromodel of the interconnect can be efficiently extracted by cascading several configuration-oriented coupled transmission lines (CCTL). Two examples are used to demonstrate the validity of the proposed approach. One is the equivalent models for differential pairs crossing an asymmetrical ground slot. The other is the crosstalk behavior prediction for a three-coupled microstrip line. The accuracy in broadband frequency range of the synthesized models of these two examples are checked both in time and frequency domain and compared with the direct-FDTD simulation. The agreement is favorably good.

Half-conductive coupling interconnection technology for digital transmission between CMOS chips

This paper describes how to use half-conductive coupling (HC-coupling) to obtain digital interconnections between two flip-chip standard CMOS integrated circuits. For process simplicity, the HC-layer can be unpatterned and the CMOS chips do not require any post-processing steps. Measurements of a complete HC-coupling, digital communication link show reliable operation up to 100 Mb/s channel speed. The two flipped prototype CMOS chips were fabricated in 0.8-/spl mu/m, 5-V CMOS. The I/O pads' pitch was 150 /spl mu/m.

Highly Accurate Quasi-Static Modeling of Coupled Interconnects in CMOS Technology

A new analytic model is presented (the model is based on the induced current density distribution inside silicon substrate) to calculate frequency dependent mutual inductance and resistance per unit length of coupled on-chip interconnects in CMOS technology. The validity of the proposed model has been checked by a comparison with a quasi-TEM spectral domain numerical simulation and equivalent-circuit modeling procedure. It is found that the silicon semiconducting substrate skin effect must be considered for the accurate prediction of the high-frequency characteristics of VLSI interconnects.

A multilevel parasitic interconnect capacitance modeling and extraction for reliable VLSI on-chip clock delay evaluation

This paper describes fringing and coupling interconnect capacitance models which include the nonlinear second-order effects of field interactions among multilevel parasitic interconnects for accurate circuit simulations. They are fitted well with numerical solutions by using a Poisson equation solver. A reliable parasitic distributed resistance-inductance-capacitance (RLC) extraction method is identified by using the solver with the bounded local three-dimensional (3-D) numerical analysis to reduce excessive central processing unit (CPU) time compared to full 3-D numerical simulation. We investigate the impact of input slew variations on the traversal clock delay within the slow ramp region of the driver gate as well as in the extracted parasitic interconnect networks. Input slew is found to be a dominant factor affecting clock delay sensitivity. In addition, we use indirect on-chip electron beam probing to confirm that the simulated clock delays are in reasonable agreement with the measured delays.

Parasitic Capacitances and Inductances for Multilevel Interconnections on GaAs-Based Integrated Circuits

A computer-efficient algorithm to determine the parasitic capacitances and inductances associated with high-density multilevel interconnections on GaAs-based integrated circuits is presented. The self and coupling interconnection capacitances have been determined by an efficient and more flexible network analogue method developed for the finite dimension interconnection configurations as well as by the method of moments in conjunction with a Green's function appropriate for the geometry of the interconnection lines. The Green's function was obtained by using the method of multiple images. The results include the fringing fields as well as the shielding by the neighboring interconnections. For a given set of the interconnection dimensions, the algorithm takes less than 30 seconds of computer processing time on a mainframe computer equipped with a math co-processor. The algorithm has been used to study the dependences of the interconnection capacitances and inductances on the interconnection parameters such...

Modelling of parasitic interconnection inductances on the GaAs-based VLSIC's

Parasitic inductances associated with the interconnections in high density environments have become one of the primary factors in the evolution of the high speed VLSI technology. We have carried out a computer-efficient simulation and developed the related computer software to determine the parasitic inductances associated with the single-, bi- and tri-level high density interconnections on the GaAs-based VLSIC's. The self and coupling interconnection inductances have been determined by a network analogue method developed for the finite-length interconnections, open substrates and finite dimensions of the bottom ground plane. Related computer software modules have been developed and run successfully on the mainframe computers. For a given set of the interconnection dimensions and other parameters, the algorithm takes less than 1 minute of the computer processing time on a mainframe computer. The modules have been used to study the dependences of the parasitic inductances on the interconnection parameters such as their length, width, separation, interlevel distance and the substrate thickness.

PCSIGV: a student-oriented program for calculating the parasitic capacitances for single-level interconnections on GaAs-based VLSI

A microcomputer-efficient algorithm to study the parasitic capacitances associated with high-density single-level interconnections on GaAs-based VLSI is presented and a student-oriented program called PCSIGV is discussed. The algorithm uses the method of moments in conjunction with a Green's function appropriate to the geometry of the interconnections. Results include the fringing fields as well as the effects of shielding due to the presence of the neighboring interconnection lines. PCSIGV has been used to study the dependence of the ground and coupling interconnections capacitances on various interconnection parameters.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

Modelling of crosstalk among the GaAs-based VLSI interconnections

We have developed a computer-efficient model and carried out computer simulations of the crosstalk effects in the single-, bi- and trilevel high-density interconnections on the GaAs-based VHSIC. The self and coupling interconnection capacitances used in the model have been determined by a network analogue method developed for the finite-length interconnections, open substrates and finite dimensions of the bottom ground plane, as well as by the method of moments in conjunction with a Green&apos;s function appropriate for the geometry of the interconnections. The Green&apos;s function was obtained by using the method of multiple images. The results include the fringing fields, as well as the shielding by the neighbouring interconnections. Related software modules have been developed and run successfully on the mainframe computers. For a given set of the interconnection dimensions and other parameters, the algorithm takes less than 5 minutes of the computer processing time on a mainframe computer. The modules have been used to study the dependences of the crosstalk voltage on the interconnection dimensions such as their lengths, widths, separations and the interlevel distances. Dependence of the crosstalk signal on other parameters such as the driving transistor resistance and the load capacitance has also been investigated. The results can be utilised to obtain optimum values for the various interconnection parameters for minimum crosstalk.