Design Of Counter Research Articles

Reliable Synchronous and Asynchronous Counter Design in QCA

Due to rapid growth in the integrated circuit (IC) industry, the demand for compact digital system design is high. However, the continued technology reductions made the feasibility of further scaling down transistor size more challenging. In response to the growing demand for ultra-compact IC designs, the revolutionary quantum-dot cellular automata (QCA) technology has emerged as a promising solution. In a digital era, the counters are widely adopted in the peer-to-peer process flow to establish a mechanism for generating unique values for each identifier/number. In this work, a unique synchronous and asynchronous counters architecture is proposed with a reliable D and T flip-flop design. The proposed QCA architecture is implemented and validated with the QCA designer tool. Furthermore, in QCA technology, unreliable QCA designs can lead to frequent errors and malfunctions in the implemented logic. To overcome this challenge, the proposed design prioritizes cell placement (the relative positions of QCA cells) to make the circuit more robust. As a result, the circuit can still produce the expected functionality even if some QCA cells malfunction. Hence, to ensure the reliability of the proposed QCA architecture, the missing cell defect analysis is carried out in comparison with existing state-of-the-art designs. Based on comparison results, the unique designs like the proposed multiplexer, D flip-flop and T flip-flop design exhibit success rates of 67.28, 77.04 and 85.15%, respectively. The experimental results demonstrate that the proposed counter-architecture outperforms existing architectures.

Simulation study for design of long counter for standard neutron fields from 1keV to 20MeV at NMIJ/AIST.

A De-Pangher-type long counter was designed for neutron measurements in standard neutron fields based on the results of simulations using the MCNP6 code at the National Metrology Institute of Japan, the National Institute of Advanced Industrial Science and Technology. The effects of six parameters in the design on the energy response of the long counter were investigated. The energy response was then quantitatively evaluated for eight design candidates selected from the investigation. The calculation results show that these candidates have a flatter energy response from 100eV to 10MeV compared to that of the current long counter. These candidates also reduce the difference between the average energy response from 10eV to 1MeV and that from 10 to 20MeV.

Design and Production of Heartbeat Counter for Medical Application

Heartbeat pulse measurement is an important medical practice used to determine the health status of an individual. This research was concerned on the design and production of heartbeat pulse counter for medical applications with specific features. The device senses and monitors the heartbeat rate whenever a fingertip is placed on the pulse sensor, the pulse sensor is a plug and play device which is detachable from the Arduino Uno board, the Arduino Uno receives and calculates this data and the result displayed on the 16X2 LCD display based on the written codes. It has the features for initial display, showing system on and when a finger is placed, it readily displays heartbeat rate detected and presents the pulse rate of the individual. Its design and production was achieved and used to test the heartbeat of many persons. Further work is required to incorporate GSM module with the capability of sending text message and cloud hosting of the medical data of an individual.

Performance improvement studies of axially partitioned dual band magnetically insulated line oscillator

In magnetically insulated line oscillator (MILO)s, a proportion of device current is responsible for the self-generated magnetic field that aids electron flow confinement in the anode cathode gap, thereby suitable RF generation. The device currents should not be high due to its direct impact on device efficiency, and electron energy depositions at load can lead to anode plasma formation. Also, the lower currents can facilitate the device to operate at larger voltages and/or for longer operational times. In this article, couple of axially partitioned dual band MILOs (DBMILO) designs that operate at lower device currents in comparison with the existing axially partitioned DBMILOs in the literature is presented. For one design with the radius of the slow wave structure (SWS), i.e., RSWS = 40 mm, the injection of the DC electron beam parameters 505 kV and 49 kA, generated an output RF power of ∼5.8 GW oscillating at 3.71 and 10.16 GHz (S-and X- bands) concurrently with ∼23.8% conversion efficiency. However, the other design (RSWS = 40.6 mm) at beam voltage 505 kV and device current of 47 kA generated an output RF power of >3.85 GW oscillating at 3.5 and 10.5 GHz, concurrently, where the frequencies are harmonically related. Thus, the proposed designs yielded significant device current reduction to ∼47 and ∼49 kA from ∼56 kA (existed), respectively, thereby drop of 16% and 12.5% to its counter designs, respectively. Also, there is substantial reduction in the electron energy depositions, thus the occurrence of anode plasma formations. Moreover, the peak conversion efficiency is enhanced to 23.4% and 16.4%, from 12.8%.

New Programmable LFSR Counters with Automatic Encoding and State Extension

An efficient method for detecting the end of a count of a linear feedback shift register (LFSR) is presented. We show how this detector can be used to extend a maximum-length LFSR sequence by a number of states up to one less than the degree of the polynomial. In addition, a new algorithm is proposed to encode binary sequence values into their corresponding LFSR sequence states. Based on this algorithm and an alternative second method, two novel programmable, full-range, high-speed LFSR counter designs are proposed. The time complexity of the conversion algorithms ranges from quadratic to exponential time in the degree of the underlying polynomial. The proposed counter solutions are fully synchronous and can be implemented with standard cells, enabling easy portability across technologies. As the levels of logic are independent of the counter size, high scalability is facilitated. For evaluation, all the designs, including the recreated state-of-the-art solution, have been implemented on an FPGA, and also simulated targeting TSMC’s N3 CMOS process node for a wide range of counter sizes. The results confirm the superiority of the proposed solutions over the state of the art in terms of frequency, area and power efficiency as the counter is scaled up.

Electronic Technology Teaching Practice Assisted by Information Technology--Taking Counter Design as an Example

Electronic Technology Teaching Practice Assisted by Information Technology--Taking Counter Design as an Example

A closer look at refusers’ counters: Benefactive changes, design constraints, and interpersonal implications

This paper examines an understudied way of refusing: counters, i.e. utterances which do not only block one course of action but put forward an alternative. An interactional approach to pragmatic meaning was taken to examine the content, design, and interpersonal implications of counters in (semi-)informal future-action negotiations. Regarding their content, it was found that counters can retain the distribution of cost/benefit of initial proffers (neutral), change them to the refuser's benefit (egoistic), or change them to the profferer's benefit (altruistic). Regarding their design, it was found that counters can be formatted as either interpersonally delicate or non-delicate actions – irrespective of their content. This suggests that specific benefactive chances are not intrinsically associated with specific interpersonal effects, e.g. egoistic and altruistic counters do not necessarily indicate interpersonal trouble or guarantee harmony, respectively. Rather, it is the design which has particular interpersonal implications, with counters formatted as non-delicate actions being hearable as problematising and/or treated as problematic. It is furthermore argued that counters are more constrained in terms of design than initial proffers – which may be formatted as non-delicate without negative interpersonal implications – and that this constraint results from their sequential position and the prior speaker's right to make a proffer.

PROPORTIONAL DETECTORS OF GAMMA-RADIATION BASED ON HIGH PURITY XENON GAS FOR RADIATION MONITORING

This article is dedicated to a detailed investigation of properties of a proportional counter based on the Xe+2%CH4 mixture. A setup for filling the detectors with high purity Xe gas and Xe-based gas mixtures was designed and made. An optimized design of the proportional counters was developed and investigated. The design parameters, such as the material and diameter of the anode, the number and material of the gas mixture inlets, composition and pressure of the gas were improved. The operating regimes of the proportional counters, as well as their thermal stability, were investigated.

A high speed and power efficient multiplier based on counter-based stacking

<span>High speed and competent addition of various operands is an essential operation in the design any computational unit. The swiftness and power competence of multiplier circuits plays vital role in enlightening the overall performance of microprocessors. Multipliers play crucial role in the design of <a name="_Hlk140074299"></a>arithmetic logic unit (ALU) or any digital signal processor (DSP) that are effectively employed for filtering and convolution operations. The process of multiplication either binary numbers or fixed-point numbers yields in enormous partial products that are to be added to get final product. These partial products in number and the process of summing up partial products dictate the latency and power consumption of the multiplier design. Here, we present a novel binary counter design that hires stacking circuits, that groups all logic “1” bits as one, followed by a novel symmetric method to merge pairs of 3-bit stacks into 6-bit stacks and then changes them to binary counts. This results in drastic improvements in power and area utilization of the multiplier. Additionally, this paper also focuses on implementation of novel approximate compressor and exploits the same for the design of approximate multipliers that can be effectively employed in any electronic systems that are characterized by power and speed constraints.</span>

Design of Automatic Truck Axle Counter Using Deep Learning on NVIDIA Jetson Nano

Design of Automatic Truck Axle Counter Using Deep Learning on NVIDIA Jetson Nano

Particle Counter Design Upgrade for Euro 7

This research article presents an optimized approach to enhance the performance of the APC exhaust gas particle analyzer, a significant instrument used for exhaust emission evaluation in diesel-powered vehicles considering EU regulations on pollutant emissions. The study aimed to address the challenge of particle counter contamination that often occurs during frequent exhaust gas measurements and leads to measurement interruptions until maintenance is conducted. To achieve this, a preparatory unit that extends the operational duration of the measurement system between maintenance intervals while preserving measurement accuracy was developed based on actual exhaust gas experiments. The preparatory unit comprises a condensate drainage system, cooling fan, HEPA filter, membrane pump, and interconnecting pipelines to prevent moisture and larger particle deposition, ensuring uninterrupted and accurate exhaust gas measurements. The research findings underscore the significance of reliable and precise exhaust gas emission measurements, contributing to advancements in particle counting technology and facilitating compliance with emissions regulations in various scientific and industrial applications. This study provides an objective representation of the proposed preparatory unit’s effectiveness in mitigating particle contamination with only 1.9% measurement variance, offering promising implications for the improvement of exhaust gas analysis methods.

Adiabatic technique based low power synchronous counter design

<p>The performance of integrated circuits is evaluated by their design architecture, which ensures high reliability and optimizes energy. The majority of the system-level architectures consist of sequential circuits. Counters are fundamental blocks in numerous very large-scale integration (VLSI) applications. The T-flip-flop is an important block in synchronous counters, and its high-power consumption impacts the overall effectiveness of the system. This paper calculates the power dissipation (PD), power delay product (PDP), and latency of the presented T flip-flop. To create a 2-bit synchronous counter based on the novel T flip-flops, a performance matrix such as PD, latency, and PDP is analyzed. The analysis is carried out at 100 and 10 MHz frequencies with varying temperatures and operating voltages. It is observed that the presented counter design has a lesser power requirement and PDP compared to the existing counter architectures. The proposed T-flip-flop design at the 45 nm technology node shows an improvement of 30%, 76%, and 85% in latency, PD, and PDP respectively to the 180 nm node at 10 MHz frequency. Similarly, the proposed counter at the 45 nm technology node shows 96% and 97% improvement in power dissipation, delay, and PDP respectively compared to the 180 nm at 10 MHz frequency.</p>

Multiple-Controlled Toffoli and Multiple-Controlled Fredkin Reversible Logic Gates-Based Reversible Synchronous Counter Design

The counters that change their transition using a clock signal are called synchronous counters. While designing a synchronous counter circuit, the power consumption and the delay are the major issues. Several synchronous counters were designed previously with the help of flip flops, but they did not provide good results. The existing synchronous counters increased power consumption and delay and decreased the speed. To overcome these issues, in this manuscript, a reversible synchronous counter is designed utilizing Multiple-Controlled Toffoli (MCT) and Multiple-Controlled Fredkin (MCF) reversible logic gates. Here, three JK flip-flop designs, such as JK1, JK2, and JK3 are designed for a reversible synchronous counter. Then JK1 and JK2 are structured by MCT. Whereas the JK3 flip-flop design is designed under MCF reversible logic gates. Coding is carried out Verilog, and then the proposed Reversible synchronous counter design (RSCD) is synthesized and implemented on FPGA using a Xilinx ISE 14.5 System generator. Here, performance metrics, such as delay, power, maximum counting rate, and total equivalent gate counts are examined. The efficiency of the proposed RSCD-MCT-MCF design attains gate counts of 23.45%, 28.94%, and 29.04% and is compared to the existing designs, such as Effective Designing of Reversible Synchronous Counters in Nanoscale (SCD-MTG), effective designing for reversible sequential circuits (SCD-3TG-4FG), designing of synchronous decimal counter utilizing reversible Toffoli–FredkinNetlist (SCD-TOF2).

Role of IoT in Crowd Management using Bidirectional Attendance Counter

Abstract: Crowd management is one of the most challenging tasks in public spaces like airports, train stations, and stadiums. The advent of the Internet of Things (IoT) has made it possible to automate the crowd management process. Bidirectional attendance counters are IoT devices that can help monitor the number of people entering and leaving a specific location. This paper discusses the role of IoT in crowd management using bidirectional attendance counters. The paper explains the design and working of the bidirectional attendance counter and how it can be used to manage crowds in public spaces.

Design of a compact long counter with an improved response using multiple point-like thermal neutron counters

Design of a compact long counter with an improved response using multiple point-like thermal neutron counters

Creation of a Framework and a Corresponding Tool Enabling the Test-Driven Development of Microservices

Microservice architectures have emerged as counter design to traditional monolithic applications. While monoliths are single executable applications, microservice architectures consist of several smaller units. Advantages of microservice architectures are their development speed, lower costs of change, and dynamic scaling ability. However, this pattern requires an adaptation of quality assurance measures. In this research article, test-driven development is investigated in context of microservices that are developed according to established practices. Based on the systems development research methodology, recommendable practices and testing strategies are examined with a translation of that knowledge into an extensive artifact, enabling test-driven microservice development on local systems. Five design principles could be identified, including focusing small services, domain-driven design, striving for low-complexity networks, avoiding cyclic dependencies, and aiming for high connectivity performance. Integration, component, and contract tests could be integrated for automatic execution, showing that test-driven development for microservices is feasible, although with room for improvements.

Delay-efficient 4:3 counter design using two-bit reordering circuit for high-speed Wallace tree multiplier

<span lang="EN-US">In many signal processing applications, multiplier is an important functional block that plays a crucial role in computation. It is always a challenging task to design the delay optimized multiplier at the system level. A new and delay-efficient structure for the 4:3 counter is proposed by making use of a two-bit reordering circuit. The proposed 4:3 counter along with the 7:3 counter, full adder (FA), and half adder (HA) circuits are employed in the design of delay-efficient 8-bit and 16-bit Wallace tree multipliers (WTMs). Using Xilinx Vivado 2017.2, the designed circuits are simulated and synthesized by targeting the device ‘xc7s50fgga484-1’ of Spartan 7 family. Further, in terms of lookup table (LUT) count, critical path delay (CPD), total on-chip power, and power-delay-product (PDP), the performance of the proposed multiplier circuit is compared with the existing multipliers.</span>

Irrigation design from below

Although often ignored or belittled by irrigation engineers and development planners, vernacular and counter designs in irrigation should be considered as valuable and complementary to the mainstream approaches of engineers and planners.

Optimal design of the neutron multiplicity counter based on metaheuristic algorithm

The neutron multiplicity measurement and analysis method is a very important measurement and analysis method in the field of international arms control verification and nuclear safeguards, and its measurement accuracy depends to some extent on detector performance. In this paper, several newer current metaheuristic algorithms are introduced to achieve neutron multiplicity counter layout optimization by combining with MC (Monte Carlo) simulation software. The algorithm with the best finding ability is selected for the optimization of another detector layout. Based on the optimization results, k-means clustering analysis is introduced so that the optimized structure can be applied to neutron multiplicity measurements. The results show that the metaheuristic algorithm has good application capability for neutron detector layout optimization and can be further investigated.

Design and performance study of a proportional counter for low-energy X-rays

A cylindrical proportional counter based on a noble gas was designed to accurately measure low-energy X-ray radiation. The detection capability of the proportional counter with different gases and geometries was calculated through the Monte Carlo method. The optimal filling gas and applicable pipe diameter were determined according to the results of the Monte Carlo simulation. Then, energy calibration was performed at the monoenergetic X-ray radiation facility (MXRF) based on Bragg diffraction, and the energy calibration results were verified using the radionuclides 241Am and 129I. The relative deviation of the theoretical and measured values of the energy does not exceed 1.4%, and the energy resolution of the designed proportional counter is approximately 10%. It was proved that the linearity of the channel and energy of the proportional counter can be used for energy spectrum analysis, and the proportional counter has a good radionuclide recognition capability. Finally, the detection efficiency of the designed proportional counter was simulated and verified at multiple energy points. A detection efficiency calculation model was established through MCNP5, and the detection efficiency of the proportional counter was measured at the MXRF. The results of the experiment and simulation showed that the proportional counter could reach a highest detection efficiency of 92% in the low-energy region. The average deviation between the experiment and simulation was 1.63% at 10–34 keV and 3.90% at 34–75 keV. The proportional counter can be used for measurement and application of X-rays in the low-energy region.