Core Memory Research Articles

Altered Hippocampal Resting-state Functional Connectivity in Highly Superior Autobiographical Memory

Individuals with Highly Superior Autobiographical Memory (HSAM) provide the opportunity to investigate the neurobiological substrates of enhanced memory performance. While previous studies started to assess the neural correlates of memory retrieval in HSAM, here we assessed for the first time the intrinsic connectivity of a core memory region, the hippocampus, with the whole brain, in 8 HSAM subjects (HSAMs) and 21 controls during resting-state functional neuroimaging. We found in HSAMs vs. controls disrupted hippocampal resting-state functional connectivity (rsFC) with high-level control regions belonging to the saliency network (the anterior cingulate cortex and the left and right insulae), and to the ventral fronto-parietal attentional network (the temporo-parietal junction and the inferior frontal gyrus), also involved with salience detection. Conversely, HSAMs showed enhanced hippocampal rsFC with sensory regions along the fusiform gyrus and the inferior temporal cortex. This altered pattern of hippocampal rsFC might be interpreted as a reduced capability of HSAMs to discriminate and select salient information, with a subsequent increase in the probability to encode and consolidate sensory information irrespective of their task-relevancy. Ultimately, these findings provide evidence that HSAM might be paradoxically enabled by an altered hippocampal rsFC that bypasses regions involved with salience detection in favor of specialized sensory regions.

High performance computing and inverse problems in acoustics and structural acoustics

Engineering applications in acoustics and structural acoustics commonly require finite element models with large numbers of degrees of freedom. Examples include applications with infinite and semi-infinite domains, as well as problems at high frequency (e.g., ultrasound) where the number of wavelengths in the domain becomes large. The finite element solution of such problems, and their inclusion inside an optimization loop for inverse problems, inevitably involves large numbers of degrees of freedom and systems of equations. Modern high-performance computing is enabling numerical solutions of acoustics applications that were previously intractable. In this talk, we will present an overview of massively parallel acoustic and structural acoustic solution capabilities in Sandia’s Sierra-SD (Structural-Dynamics) software. Sierra-SD is a massively parallel finite element application for structural dynamics and acoustics, having recently demonstrated the implicit solution of models with over 2 × 109 degrees of freedom and running on up to one hundred thousand distributed memory cores. Domain decomposition and MPI parallelism are used to split a large domain into many small domains that can be solved in parallel. Large-scale applications in ship shock loading and vibration of reentry bodies will be shown as demonstrations. [SNL is managed and operated by NTESS under DOE NNSA Contract DE-NA0003525.]

Epigenetic scarring of exhausted T cells hinders memory differentiation upon eliminating chronic antigenic stimulation.

Exhausted CD8 T cells (TEX) are a distinct state of T cell differentiation associated with failure to clear chronic viruses and cancer. Immunotherapies like PD-1 blockade can re-invigorate TEX cells, but re-invigoration is not durable. A major unanswered question is whether TEX cells differentiate into functional durable memory T cells (TMEM) upon antigen clearance. Here, using a mouse model, we found that upon eliminating chronic antigenic stimulation, TEX cells partially (re)acquire phenotypic and transcriptional features of TMEM cells. These “recovering” TEX cells originated from the T-cell factor (TCF-1+) TEX progenitor subset. Nevertheless, the recall capacity of these recovering-TEX cells remained compromised compared to TMEM cells. Chromatin-accessibility profiling revealed failure to recover core memory epigenetic circuits and maintenance of a largely exhausted open chromatin landscape. Thus, despite some phenotypic and transcriptional recovery upon antigen clearance, exhaustion leaves durable epigenetic scars constraining future immune responses. These results support epigenetic remodeling interventions for TEX cell targeted immunotherapies.

Theoretical investigation on the buckling behavior of smart composite sandwich panels with viscoelastic core and shape memory alloy included skins

AbstractToday, due to the undeniable importance of smart materials such as shape memory alloys (SMAs), their application in engineering structures has become widespread. So, investigating their various properties is the subject of many studies. According to Reddy's higher‐order shear deformation theory and von Kármán nonlinearity, this research presented the buckling characteristics of SMA composite sandwich panel with a viscoelastic core. The governing equations of the panel are derived by implementing Hamilton's principle. For investigating the accuracy, this article is validated with other previous researches, and a good correlation is observed between the results. Finally, different parameters such as volume fraction of SMA, the thickness of the viscoelastic core, geometry ratios, and magnetic fields are considered in this article. The results show that the critical buckling response decreased by increasing the magnitude of magnetic potential. But it has a small influence on the real part of the critical buckling load of sandwich composite panel.

Router1x3 Protocol Design Implementation and Verification with Virtual Cut through Mechanism for Network on Chip (NoC)

Hundreds of processors and memory cores are implemented on a single substrate called the System on Chip (SoC). The SoC with bus-based architecture has restrictions on the processing speed of the system and as the design becomes complex and the issue of scalability arises. Hence NoC is designed to enhance the scalability, data reliability, and processing speed with low power consumption by decoupling communication from computations [1]. Using NoC the IP cores of SoC are connected through on-chip routers and send data to each other through packet switching. The router is a processing chip that decides the right path for data transmission, hence the efficient design of the router is essential to enhance the performance and throughput of the system [2]. To reduces latency through the switch, the Virtual cut-through mechanism is a packet switching technique, in which the switch starts forwarding a packet as soon as the destination address is processed by header. Hence the present work focuses on a router input-output protocol design with the Virtual Cut-through mechanism for closed-loop communication. Router 1x3 has a single input port and three output ports. The architecture of Router 1x3 with sub-modules such as FIFO, FSM, Synchronizer, and Register is designed analyzed and verified using Verilog, System Verilog language, and Universal Verification Methodology(UVM). And it is also implemented on Xilinx 14.5 IDE with Spartan-6- XC6SLX45 FPGA.

Mansard Roofline Model: Reinforcing the Accuracy of the Roofs

Continuous enhancements and diversity in modern multi-core hardware, such as wider and deeper core pipelines and memory subsystems, bring to practice a set of hard-to-solve challenges when modeling their upper-bound capabilities and identifying the main application bottlenecks. Insightful roofline models are widely used for this purpose, but the existing approaches overly abstract the micro-architecture complexity, thus providing unrealistic performance bounds that lead to a misleading characterization of real-world applications. To address this problem, the Mansard Roofline Model (MaRM), proposed in this work, uncovers a minimum set of architectural features that must be considered to provide insightful, but yet accurate and realistic, modeling of performance upper bounds for modern processors. By encapsulating the retirement constraints due to the amount of retirement slots, Reorder-Buffer and Physical Register File sizes, the proposed model accurately models the capabilities of a real platform (average rRMSE of 5.4%) and characterizes 12 application kernels from standard benchmark suites. By following a herein proposed MaRM interpretation methodology and guidelines, speed-ups of up to 5× are obtained when optimizing real-world bioinformatic application, as well as a super-linear speedup of 18.5× when parallelized.

Design and simulation of high-speed and low-power memcapacitor-based nonvolatile static cells using FinFET transistors

Metal–oxide–semiconductor field-effect transistors (MOSFETs) are mostly used in the design of static cells. MOSFETs have disadvantages, such as increased leakage current, reduced reliability, increased short-channel effects, and large changes in parameters. In this paper, fin field-effect transistors (FinFETs) are used instead of MOSFETs. Memristive elements are used in the design of a nonvolatile static cell. The memory cell presented here includes a static random access memory (SRAM) core (a 6T FinFET cell in this case) with two memristors and two memcapacitors, thus making a 6T FinFET SRAM cell-based 2R2C. The designed nonvolatile memory cell performed better in terms of power consumption, energy, areal factors, static noise margin, write margin, and read/write propagation delay than other designs presented so far. The figures of merit of the proposed design are also substantially improved, making the presented scheme a better approach for ‘read-write’ operations. In this paper, we have tried to keep the load capacitance ( as small as possible to improve the power consumption and the write and read delays, because the capacitor charge has a direct relationship with the cell’s power consumption.

Optimizing MultiStack Parallel (MSP) Sorting Algorithm


 
 
 Mobile smartphones/laptops are becoming much more powerful in terms of core count and memory capacity. Demanding games and parallel applications/algorithms can hopefully take advantages of the hardware. Our parallel MSPSort algorithm is one of those examples. However, MSPSort can be optimized and fine tuned even further to achieve its highest capabilities. To evaluate the effectiveness of MSPSort, two Linux systems are quad core ARM Cortex-A72 and 24-core AMD ThreadRipper R9-2920. It has been demonstrated that MSPSort is comparable to the well-known parallel standard template library sorting functions, i.e. Balanced QuickSort and Multiway MergeSort in various aspects such as run time and memory requirements.
 
 

Silent-PIM: Realizing the Processing-in-Memory Computing With Standard Memory Requests

The Deep Neural Network (DNN), Recurrent Neural Network (RNN) applications, rapidly becoming attractive to the market, process a large amount of low-locality data; thus, the memory bandwidth limits their peak performance. Therefore, many data centers actively adapt high-bandwidth memory like HBM2/HBM2E to resolve the problem. However, this approach would not provide a complete solution since it still transfers the data from the memory to the computing unit. Thus, processing-in-memory (PIM), which performs the computation inside memory, has attracted attention. However, most previous methods require the modification or the extension of core pipelines and memory system components like memory controllers, making the practical implementation of PIM very challenging and expensive in development. In this article, we propose a Silent-PIM that performs the PIM computation with standard DRAM memory requests; thus, requiring no hardware modifications and allowing the PIM memory device to perform the computation while servicing non-PIM applications' memory requests. We can achieve our design goal by preserving the standard memory request behaviors and satisfying the DRAM standard timing requirements. In addition, using standard memory requests makes it possible to use DMA as a PIM's offloading engine, resulting in processing the PIM memory requests fast and making a core perform other tasks. We compared the performance of three Long Short-Term Memory models (LSTM) kernels on real platforms, such as the Silent-PIM modeled on the FPGA, GPU, and CPU. For (p ×512) ×(512 ×2048) matrix multiplication with a batch size p varying from 1 to 128, the Silent-PIM performed up to 16.9x and 24.6x faster than GPU and CPU, respectively, p=1, which was the case without having any data reuse. At p=128, the highest data reuse case, the GPU performance was the highest, but the PIM performance was still higher than the CPU execution. Similarly, at (p ×2048) element-wise multiplication and addition, where there was no data reuse, the Silent-PIM always achieved higher than both CPU and GPU. It also showed that when the PIM's EDP performance was superior to the others in all the cases having no data reuse.

NBBS: A Non-Blocking Buddy System for Multi-Core Machines

Common implementations of core memory allocation components handle concurrent allocation/release requests by synchronizing threads via spin-locks. This approach is not prone to scale, a problem that has been addressed in the literature by introducing layered allocation services or replicating the core allocators---the bottom-most ones within the layered architecture. Both these solutions tend to reduce the pressure of actual concurrent accesses to each individual core allocator. In this article, we explore an alternative approach to scalability of memory allocation/release, which can be still combined with those literature proposals. We present a fully non-blocking buddy system, where threads performing concurrent allocations/releases do not undergo any spin-lock based synchronization. Our solution allows threads to proceed in parallel, and commit their allocations/releases unless a conflict is materialized while handling the allocator metadata---memory fragmentation and coalescing is also carried out in a fully non-blocking manner. Conflict detection relies in our solution on atomic Read-Modify-Write (RMW) machine instructions, guaranteed to execute atomically by the processor firmware. We also provide a proof of the correctness of our non-blocking buddy system and show the results of an experimental study that outlines the effectiveness of our solution.

MESI protocol for multicore processors based on FPGA

In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultaneously for more than one task or all the cores working in parallel for the same task. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So, if one core requests a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores. This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using VHDL coding and implemented using ISE Xilinx software, one protocol was used in this design, the MESI (Modify, Exclusive, Shared and Invalid) protocol. Test results were taken by using test bench, and showed all the states of the protocols are working correctly.

MESI protocol for multicore processors based on FPGA

In modern techniques of building processors, manufactures using more than one processor in the integrated circuit (chip) and each processor called a core. The new chips of processors called a multi-core processor. This new design makes the processors to work simultaneously for more than one task or all the cores working in parallel for the same task. All cores are similar in their design, and each core has its own cache memory, while all cores shares the same main memory. So, if one core requests a block of data from main memory to its cache, there should be a protocol to declare the situation of this block in the main memory and other cores. This is called the cache coherency or cache consistency of multi-core. In this paper a special circuit is designed using VHDL coding and implemented using ISE Xilinx software, one protocol was used in this design, the MESI (Modify, Exclusive, Shared and Invalid) protocol. Test results were taken by using test bench, and showed all the states of the protocols are working correctly.

Activities of daily living and working memory in pediatric attention-deficit/hyperactivity disorder (ADHD)

ABSTRACT Most children with ADHD have impaired working memory abilities. These working memory deficits predict impairments in activities of daily living (ADLs) for adults with ADHD. However, our understanding of the relation between pediatric ADHD and ADLs is limited. Thus, this study aimed to examine (1) the extent to which pediatric ADHD is associated with ADL difficulties; and if so (2) the extent to which these difficulties are related to their well-documented working memory difficulties and/or core ADHD inattentive and hyperactive/impulsive symptom domains. A well-characterized, clinically evaluated sample of 141 children ages 8–13 years (M = 10.36, SD = 1.46; 51 girls; 70% White/non-Hispanic) were administered a battery of well-validated working memory tests and assessed for ADHD symptoms (teacher-ratings) and ADL difficulties (parent-ratings); cross-informant reports were used to control for mono-informant bias. Children with ADHD exhibited medium magnitude difficulties with ADLs (d = 0.61, p < .005, 38% impaired). Results of the bias-corrected, bootstrapped conditional effects model indicated that lower working memory predicted reduced performance of age-expected ADLs (β =0.28) and greater ADHD inattentive (β = −0.40) and hyperactive/impulsive symptoms (β = −0.16). Greater inattentive, but not hyperactive/impulsive, symptoms predicted greater ADL difficulties (β = −0.36) even after controlling for working memory. Interestingly, working memory exerted a significant indirect effect on ADLs via inattentive (indirect effect: β = 0.15, effect ratio = .54) but not hyperactive/impulsive symptoms. These findings implicate ADHD inattentive symptoms as a potential mechanism underlying ADL difficulties for children with ADHD, both independently and via working memory’s role in regulating attention.

Event-Based but Not Time-Based Prospective Memory Is Related to Oral Health in Late Adulthood

Background: Most evidence now indicates that cognitive function is related to poorer oral health in late adulthood, but that this relationship is not invariant across specific cognitive domains. Prospective memory (PM) is a core memory skill that refers to memory for future intentions and is known to be related to the formation of habits such as tooth flossing. However, the relationship between PM and oral health has been subject to only limited empirical study. Objective: The two studies reported in this paper were designed to test whether PM is related to oral health in older adults of varying vulnerability status. Methods: Study 1 sampled community-dwelling older adults (N = 172) living independently in the community; Study 2 sampled older adults living in a retirement village (N = 32). Participants in both studies were asked to complete a behavioural measure of PM, with their oral health indexed via self-report (Study 1) or an objective oral health exam (Study 2). Results: In both studies, relationships emerged between event-based PM and oral health, with Study 2 showing that these relationships were specific to oral health measures of plaque and calculus. Conclusions: Older adults are particularly vulnerable to dental pathology, with important implications for their broader health and well-being. By showing that there is a relationship between oral health and a particular type of PM, this work will have potential implications for the development of more effective interventions focused on enhancing oral health outcomes in this group, such as those focused on strengthening habit formation.

Low power SRAM using Adiabatic Logic

In this paper the design of low power SRAM has been presented. SRAM memory cell has been realized using adiabatic logic to achieve low power operation. Adiabatic SRAM has been realized using two methods such as i) gradual charging and discharging of bit-line during writing mode and ii) utilizing control transistor based adiabatic circuit i.e., Two Phase Adiabatic Dynamic Logic (2PADL) circuit for the design of memory cell. Furthermore, energy recovery of word line and bit line charge stored in the interconnect capacitances has been realized for the benefit of energy savings. Charge recovery circuits based on 2PADL has been employed in the proposed SRAM memory core to achieve energy recovery. SRAM memory array of (4×4) has been designed as a test circuit. All the circuits are implemented using 180nm CMOS technology and simulations are carried out using Cadence® Virtuoso tool. Simulation results prove that the proposed memory cell has significant amount of energy savings when compared to the conventional static CMOS SRAM cell.

Mathematical Profile Test: A Preliminary Evaluation of an Online Assessment for Mathematics Skills of Children in Grades 1-6.

The domain of numerical cognition still lacks an assessment tool that is theoretically driven and that covers a wide range of key numerical processes with the aim of identifying the learning profiles of children with difficulties in mathematics (MD) or dyscalculia. This paper is the first presentation of an online collectively administered tool developed to meet these goals. The Mathematical Profile Test (MathPro Test) includes 18 subtests that assess numerical skills related to the core number domain or to the visual-spatial, memory or reasoning domains. The specific aim of this paper is to present the preliminary evaluation both of the sensitivity and the psychometric characteristics of the individual measures of the MathPro Test, which was administered to 622 primary school children (grades 1–6) in Belgium. Performance on the subtests increased across all grades and varied along the level of difficulty of the items, supporting the sensitivity of the test. The MathPro Test also showed satisfactory internal consistency and significant and stable correlation with a standardized test in mathematics across all grades. In particular, the achievement in mathematics was strongly associated with the performance on the subtests assessing the reasoning and the visuospatial domains throughout all school grades, whereas associations with the core number and memory tasks were found mainly in the younger children. MD children performed significantly lower than their peers; these differences in performance on the MathPro subtests also varied according to the school grades, informing us about the developmental changes of the weaknesses of children with MD. These results suggest that the MathPro Test is a very promising tool for conducting large scale research and for clinicians to sketch out the mathematical profile of children with MD or dyscalculia.

Industrial-strength OLTP using main memory and many cores

GaussDB, and its open source version named openGauss, are Huawei's relational database management systems (RDBMS), featuring a primary disk-based storage engine. This paper presents a new storage engine for GaussDB that is optimized for main memory and many cores. We started from a research prototype which exploits the power of the hardware but is not useful for customers. This paper describes the details of turning this prototype to an industrial storage engine, including integration with GaussDB. Standard benchmarks show that the new engine provides more than 2.5x performance improvement to GaussDB for full TPC-C on Intel's x86 many-cores servers, as well as on Huawei TaiShan servers powered by ARM64-based Kunpeng CPUs.

The enhancement of logging system accuracy for infrastructure as a service cloud

We introduce the novel technical results of the enhanced logging system for customer virtual machines (VMs) in an Infrastructure as a Service (IaaS) cloud. The main contribution is that the enhanced system can work with a better system's accuracy and speed, with the simplicity of the design and implementation. We measure the accuracy of the unenhanced logging system, then find a quick solution to enhance the system based on the results of the measurement. To measure and enhance the unenhanced system, we increase the main memory and CPU cores of the VMs then collect the accuracy results from each increment configuration. We analyze the results and propose to use the taskset tool to enhance the accuracy of the system. Found three main findings include: firstly, the accuracy of the enhanced system is about 20% on maximum better than the unenhanced one; the enhanced system accuracy becomes 100%; lastly, the enhanced system can detect a file with the smaller file size as almost 12% smaller. The findings can be a basis to design the logging systems in an IaaS cloud, to decrease hardware and energy investment. To the best of our knowledge, the contribution and findings are not in the literature.

Bpop: an efficient program for estimating base population allele frequencies in single and multiple group structured populations

Base population allele frequencies (AF) should be used in genomic evaluations. A program named Bpop was implemented to estimate base population AF using a generalized least squares (GLS) method when the base population individuals can be assigned to groups. The required dense matrix products involving (A22 )-1v were implemented efficiently using sparse submatrices of A-1, where A and A22 are pedigree relationship matrices for all and genotyped animals, respectively. Three approaches were implemented: iteration on pedigree (IOP), iteration in memory (IM), and direct inversion by sparsity preserving Cholesky decomposition (CHM). The test data had 1.5 million animals genotyped using 50240 markers. Total computing time (the product (A22)-11) was 53 min (1.2 min) by IOP, 51 min (0.3 min) by IM, and 56 min (4.6 min) by CHM. Peak computer core memory use was 0.67 GB by IOP, 0.80 GB by IM, and 7.53 GB by CHM. Thus, the IOP and IM approaches can be recommended for large data sets because of their low memory use and computing time.

Progressive Memory Circuit Impairments along with Alzheimer's Disease Neuropathology Spread: Evidence from in vivo Neuroimaging.

During the progression of Alzheimer's disease (AD), neuropathology may propagate transneuronally, cause disruption in memory circuit, and lead to memory impairment. However, there is a lack of in vivo evidence regarding this process. Thus, we aim to simulate and observe the progression of neuropathology in AD continuum. We included cognitively normal (CN), mild cognitive impairments (MCI), and AD subjects, and further classified them using the A/T/N scheme (Group 0: CN, A - T-; Group 1: CN, A + T-; Group 2: CN, A + T+; Group 3: MCI, A + T+; Group 4: AD, A + T+). We investigated alterations of three core memory circuit structures: hippocampus (HP) subfields volume, cingulum-angular bundles (CAB) fiber integrity, and precuneus cortex volume. HP subfields volume showed the trend of initially increased and then decreased (starting from Group 2), while precuneus volume decreased in Groups 3 and 4. The CAB integrity degenerated in Groups 3 and 4 and aggravated with higher disease stages. Further, memory circuit impairments were correlated with neuropathology biomarkers and memory performance. Conclusively, our results demonstrated a pattern of memory circuit impairments along with AD progression: starting from the HP, then propagating to the downstream projection fiber tract and cortex. These findings support the tau propagation theory to some extent.