Core Memory Research Articles

Power and performance analysis of multimedia applications running on low-power devices by cache modeling

High processing speed is required to support computation intensive applications. Cache memory is used to improve processing speed by reducing the speed gap between the fast processing core and slow main memory. However, the problem of adopting cache into computing systems is twofold: cache is power hungry (that challenges energy constraints) and cache introduces execution time unpredictability (that challenges supporting real-time multimedia applications). Recently published articles suggest that using cache locking improves predictability. However, increased cache activities due to aggressive cache locking make the system consume more energy and become less efficient. In this paper, we investigate the impact of cache parameters and cache locking on power consumption and performance for real-time multimedia applications running on low-power devices. In this work, we consider Intel Pentium-like single-processor and Xeon-like multicore architectures, both with two-level cache memory hierarchy, using three popular multimedia applications: MPEG-4 (the global video coding standard), H.264/AVC (the network friendly video coding standard), and recently introduced H.265/HEVC (for improved video quality and data compression ratio). Experimental results show that cache locking mechanism added to an optimized cache memory structure is very promising to increase the performance/power ratio of low-power systems running multimedia applications. According to the simulation results, performance can be improved by decreasing cache miss rate down to 36 % and the total power consumption can be saved up to 33 %. It is also observed that H.265/HEVC has significant performance advantage over H.264/AVC (and MPEG-4) for smaller caches.

Offshore petroleum regulatory reform: the WA experience—first 12 months in review

On 1 January 2012, a new regulatory framework for the offshore oil and gas industry in Australian Commonwealth waters started. The changes were profound and brought about a single national regulator for safety, environmental management, and well integrity. It also meant that the seven former designated authorities were abolished in favour of a single National Titles Administrator. In the lead up to the reforms, ministers Martin Ferguson and Frederick Moore agreed that officials from their respective departments would implement cooperative working arrangements for the WA adjacent offshore area, to facilitate and ensure a smooth transition for the industry and help achieve the recommendations of the Productivity Commission's review. The authors of this extended abstract reflect on and share the experiences of the past 12 months. An update of the authors' respective agencies' progress beyond the transition phase is also discussed. This extended abstract also outlines projects of interest and how they will benefit the industry and continue to develop the foundations of the cooperative working arrangements between NOPTA and WA-DMP. During the changes and transition program, industry and regulators have strived to engage in the new regime, and the results have been positive. Now is the opportunity for us to come together, ask questions, share information, and examine what has worked and what is yet to come. Several aspects of the arrangements are now evident: the establishment of the National Core Store and Data Repository, the establishment of the National Electronic Approvals and Tracking System (NEATS), and the day-to-day interactions between NOPTA and WA-DMP. The WA-DMP speaker reviews Joint Authority operations for the WA adjacent area since the establishment of NOPTA and NOPSEMA. Bill Tinapple also reviews regulatory framework developments for WA; in particular, changes to provide for shale and tight gas and oil activity, as well as, public engagement to increase confidence in regulatory processes. Coordination of regulatory processes across jurisdictional boundaries are reviewed, including case studies for Gorgon, Wheatstone, and Macedon.

Offshore petroleum regulatory reform: the Western Australian experience—first 12 months in review

On 1 January 2012, a new regulatory framework for the offshore oil and gas industry in Australian Commonwealth waters started. The changes were profound and brought about a single national regulator for safety, environmental management, and well integrity. It also meant that the seven former designated authorities were abolished in favour of a single National Titles Administrator. In the lead up to the reforms, ministers Martin Ferguson and Frederick Moore agreed that officials from their respective departments would implement cooperative working arrangements for the WA adjacent offshore area, to facilitate and ensure a smooth transition for the industry and help achieve the recommendations of the Productivity Commission's review. The authors of this extended abstract reflect on and share the experiences of the past 12 months. An update of the authors' respective agencies' progress beyond the transition phase is also discussed. This extended abstract also outlines projects of interest and how they will benefit the industry and continue to develop the foundations of the cooperative working arrangements between NOPTA and WA-DMP. During the changes and transition program, industry and regulators have strived to engage in the new regime, and the results have been positive. Now is the opportunity for us to come together, ask questions, share information, and examine what has worked and what is yet to come. Several aspects of the arrangements are now evident: the establishment of the National Core Store and Data Repository, the establishment of the National Electronic Approvals and Tracking System (NEATS), and the day-to-day interactions between NOPTA and WA-DMP. The WA-DMP speaker reviews Joint Authority operations for the WA adjacent area since the establishment of NOPTA and NOPSEMA. Bill Tinapple also reviews regulatory framework developments for WA; in particular, changes to provide for shale and tight gas and oil activity, as well as, public engagement to increase confidence in regulatory processes. Coordination of regulatory processes across jurisdictional boundaries are reviewed, including case studies for Gorgon, Wheatstone, and Macedon.

비트맵 메모리 공유를 통해 면적을 크게 줄인 효율적인 수리 방법

최근의 시스템 온 칩 (SoC) 설계 기술의 발전에 따라, 수백개의 임베디드 메모리 코어들이 칩의 대부분의 면적을 차지하고 있다. 그러므로 시스템 온 칩의 수율은 임베디드 메모리 코어들의 수율에 따라 결정된다고 볼 수 있다. 최적의 수리 효율을 가지는 built-in self repair (BISR)을 모든 메모리들이 가지고 있게 된다면 면적의 부담이 너무 크다. 본 논문에서는 이와 같은 면적의 부담을 줄이기 위하여 메모리들을 그룹화 한 후에 비트맵 메모리를 공유하여 면적 부담을 크게 줄이는 방법을 제안한다. 제안하는 비트맵 메모리 공유방법은 built-in redundancy analysis (BIRA)의 면적을 크게 줄일 수 있다. 실험결과를 통해서 보면 제안하는 방법이 면적 부담을 대략 80%정도 줄이는 것을 확인 할 수 있다.

Heavy-Ion Radiation Characteristics of DDR2 Synchronous Dynamic Random Access Memory Fabricated in 56 nm Technology

We developed a mass-memory chip by staking 1 Gbit double data rate 2 (DDR2) synchronous dynamic random access memory (SDRAM) memory core up to 4 Gbit storage for future satellite missions which require large storage for data collected during the mission execution. To investigate the resistance of the chip to the space radiation environment, we have performed heavy-ion-driven single event experiments using Heavy Ion Medical Accelerator in Chiba medium energy beam line. The radiation characteristics are presented for the DDR2 SDRAM (K4T1G164QE) fabricated in 56 nm technology. The statistical analyses and comparisons of the characteristics of chips fabricated with previous technologies are presented. The cross-section values for various single event categories were derived up to ~80 <TEX>$MeVcm^2/mg$</TEX>. Our comparison of the DDR2 SDRAM, which was fabricated in 56 nm technology node, with previous technologies, implies that the increased degree of integration causes the memory chip to become vulnerable to single-event functional interrupt, but resistant to single-event latch-up.

A CACHE DESIGN METHOD FOR SPATIAL INFORMATION VISUALIZATION IN 3D REAL-TIME RENDERING ENGINE

Abstract. A well-designed cache system has positive impacts on the 3D real-time rendering engine. As the amount of visualization data getting larger, the effects become more obvious. They are the base of the 3D real-time rendering engine to smoothly browsing through the data, which is out of the core memory, or from the internet. In this article, a new kind of caches which are based on multi threads and large file are introduced. The memory cache consists of three parts, the rendering cache, the pre-rendering cache and the elimination cache. The rendering cache stores the data that is rendering in the engine; the data that is dispatched according to the position of the view point in the horizontal and vertical directions is stored in the pre-rendering cache; the data that is eliminated from the previous cache is stored in the eliminate cache and is going to write to the disk cache. Multi large files are used in the disk cache. When a disk cache file size reaches the limit length（128M is the top in the experiment), no item will be eliminated from the file, but a new large cache file will be created. If the large file number is greater than the maximum number that is pre-set, the earliest file will be deleted from the disk. In this way, only one file is opened for writing and reading, and the rest are read-only so the disk cache can be used in a high asynchronous way. The size of the large file is limited in order to map to the core memory to save loading time. Multi-thread is used to update the cache data. The threads are used to load data to the rendering cache as soon as possible for rendering, to load data to the pre-rendering cache for rendering next few frames, and to load data to the elimination cache which is not necessary for the moment. In our experiment, two threads are designed. The first thread is to organize the memory cache according to the view point, and created two threads: the adding list and the deleting list, the adding list index the data that should be loaded to the pre-rendering cache immediately, the deleting list index the data that is no longer visible in the rendering scene and should be moved to the eliminate cache; the other thread is to move the data in the memory and disk cache according to the adding and the deleting list, and create the download requests when the data is indexed in the adding but cannot be found either in memory cache or disk cache, eliminate cache data is moved to the disk cache when the adding list and deleting are empty. The cache designed as described above in our experiment shows reliable and efficient, and the data loading time and files I/O time decreased sharply, especially when the rendering data getting larger.

Structural vibration control using a tunable hybrid shape memory material vibration absorber

Vibration absorber has been used as an effective tool in the vibration reduction of structure-suffered single-frequency excitation. However, for structures subjected to excitation with varying frequency, an absorber with actively tunable frequency capability may offer more powerful solution. In this study, an absorber that consisted of a spring element made of hybrid shape memory materials was proposed. A cantilevered beam fabricated by superelastic core and shape memory polymer sleeves was employed as the spring element of the absorber. By controlling the electric current through the superelastic core, and thereby the temperature of the shape memory polymer sleeves, the natural frequency of the absorber was tunable. The fabricated hybrid shape memory material absorber was capable of changing its natural frequency by more than 45%. Finally, vibration reduction of a cantilever structure subjected to different harmonic excitations was demonstrated using gain-scheduling control algorithm.

Probabilistic classifier: generated using randomised sub-sampling of the feature space

Nowadays supervised classification, based on the concept of pattern recognition, is an integral part of virtual screening. The central idea of supervised classification in chemoinformatics is to design a classifying algorithm that accurately assigns a new molecule to one of a set of predefined classes. Naturally, probabilistic classifiers can be far more useful than hard point classifiers in making a decision on problems [1], such as virtual screening, where there is an associated risk in classifying an instance to one class or the other. For their conceptual simplicity and computational efficiency probabilistic classification methods based on the Naive Bayes concept are widely employed in chemoinformatics. The simplicity of the Naive Bayes is due to the assumption that the descriptors representing the molecule one desires to classify are statistically independent. Unfortunately it is well documented that when the molecular descriptors are binary-valued - which is often the case in chemoinformatics - and thus take values of 0 or 1 the Naive Bayesian classifier can only act as a linear classifier in the descriptor space. Techniques such as the Parzen-Window approach can address the above shortcomings but suffer from being computationally expensive as they require one to retain all the training dataset in core memory [2,3]. In an attempt to address the above mentioned drawbacks, a new probabilistic classifier is proposed which uses randomized sub-sampling of the descriptor space. The proposed algorithm generates better class membership predictions than its Naive Bayesian counterpart on classifying molecules that are non-linearly separable in descriptor space. We present a realistic test of the new method by classifying large chemical datasets generated from the ChEMBL database [4].

A case of hyperthymesia: rethinking the role of the amygdala in autobiographical memory

Much controversy has been focused on the extent to which the amygdala belongs to the autobiographical memory (AM) core network. Early evidence suggested the amygdala played a vital role in emotional processing, likely helping to encode emotionally charged stimuli. However, recent work has highlighted the amygdala's role in social and self-referential processing, leading to speculation that the amygdala likely supports the encoding and retrieval of AM. Here, cognitive as well as structural and functional magnetic resonance imaging data was collected from an extremely rare individual with near-perfect AM, or hyperthymesia. Right amygdala hypertrophy (approximately 20%) and enhanced amygdala-to-hippocampus connectivity (>10 SDs) was observed in this volunteer relative to controls. Based on these findings and previous literature, we speculate that the amygdala likely charges AMs with emotional, social, and self-relevance. In heightened memory, this system may be hyperactive, allowing for many types of autobiographical information, including emotionally benign, to be more efficiently processed as self-relevant for encoding and storage.

Counterfactual thinking: an fMRI study on changing the past for a better future

Recent studies suggest that a brain network mainly associated with episodic memory has a more general function in imagining oneself in another time, place or perspective (e.g. episodic future thought, theory of mind, default mode). If this is true, counterfactual thinking (e.g. 'If I had left the office earlier, I wouldn't have missed my train.') should also activate this network. Present functional magnetic resonance imaging (fMRI) study explores the common and distinct neural activity of counterfactual and episodic thinking by directly comparing the imagining of upward counterfactuals (creating better outcomes for negative past events) with the re-experiencing of negative past events and the imagining of positive future events. Results confirm that episodic and counterfactual thinking share a common brain network, involving a core memory network (hippocampal area, temporal lobes, midline, and lateral parietal lobes) and prefrontal areas that might be related to mentalizing (medial prefrontal cortex) and performance monitoring (right prefrontal cortex). In contrast to episodic past and future thinking, counterfactual thinking recruits some of these areas more strongly and extensively, and additionally activates the bilateral inferior parietal lobe and posterior medial frontal cortex. We discuss these findings in view of recent fMRI evidence on the working of episodic memory and theory of mind.

Efficient Built-In Self-Repair Techniques for Multiple Repairable Embedded RAMs

In this paper, efficient built-in self-repair (BISR) techniques for multiple repairable memory cores with different sizes and divided redundancy mechanisms are proposed. Embedded memory cores are first partitioned into memory groups. For each memory group, a redundant memory module is added and divided into row blocks and column blocks. Moreover, the memory cores within a memory group are partitioned into divided arrays (consisting of row/column blocks) of the same size. The redundant memory can be shared among all memory cores within the same memory group. Therefore, unlike the traditional redundancy architectures, a row (column) block is used as the basic replacement element. Based on the proposed redundancy architecture, a heuristic heterogeneous extended spare pivoting redundancy analysis algorithm suitable for built-in implementation is also proposed. Experimental results show that the repair rate and manufacturing yield can be improved significantly due to the efficient usage of redundancy. Moreover, the area overhead of the BISR circuitry for an example memory group consisting of four memory instances of size 9.25 Mbits is only 1.12%.

An Adaptive Low-Cost Tester Architecture Supporting Embedded Memory Volume Diagnosis

This paper describes the working principle and an implementation of a low-cost tester architecture supporting volume test and diagnosis of built-in self-test (BIST)-assisted embedded memory cores. The described tester architecture autonomously executes a diagnosis-oriented test program, adapting the stimuli at run-time, based on the collected test results. In order to effectively allow the tester architecture to interact with the devices under test with an acceptable time overhead, the approach exploits a special hardware module to manage the diagnostic process. Embedded static RAMs equipped with diagnostic BISTs and IEEE 1500 wrappers were selected as case study; experimental results show the feasibility of the approach when having a field-programmable gate array available on the tester and its effectiveness in terms of diagnosis time and required tester memory with respect to traditional testers executing diagnosis procedures by means of software running on the host computer.

Culture and Posttraumatic Stress Disorder (PTSD): A Proposed Conceptual Framework

It is widely accepted that the understanding of any psychological disorder needs to be contextualised within cultural parameters. The notion that current diagnostic taxonomies are not always universally applicable does not mean that all symptoms are not applicable. We present a framework that is aimed at being a starting point from which to delineate universal and culture specific elements of PTSD. The framework follows the possible influence of cultural factors on (a) the formation of an intrusive memory, (b) an understanding of how such a memory becomes pathological, and (c) how symptoms are expressed from the intrusive memory core of PTSD. While the framework presents certain elements (e.g. intrusive memory and core schemas) as centrally important, the focus is on a heuristic framework that allows for the study of the dynamic interaction between potentially universal and cultural factors and how this interaction may produce the symptom profile generally seen with PTSD. Tentative recommendations are made for a research agenda and are presented after a brief exploration of the strengths and weaknesses of such a framework.

Adaptive Multiclient Network-on-Chip Memory Core: Hardware Architecture, Software Abstraction Layer, and Application Exploration

This paper presents the hardware architecture and the software abstraction layer of an adaptive multiclient Network-on-Chip (NoC) memory core. The memory core supports the flexibility of a heterogeneous FPGA-based runtime adaptive multiprocessor system called RAMPSoC. The processing elements, also called clients, can access the memory core via the Network-on-Chip (NoC). The memory core supports a dynamic mapping of an address space for the different clients as well as different data transfer modes, such as variable burst sizes. Therefore, two main limitations of FPGA-based multiprocessor systems, the restricted on-chip memory resources and that usually only one physical channel to an off-chip memory exists, are leveraged. Furthermore, a software abstraction layer is introduced, which hides the complexity of the memory core architecture and which provides an easy to use interface for the application programmer. Finally, the advantages of the novel memory core in terms of performance, flexibility, and user friendliness are shown using a real-world image processing application.

Evaluation of SRAM-Core Susceptibility against Power Supply Voltage Variation

The susceptibility of a static random access memory (SRAM) core against static and dynamic variation of power supply voltage is evaluated, by using on-chip diagnosis structures of memory built-in self testing (MBIST) and on-chip voltage waveform monitoring (OCM). The SRAM core of interest in this paper is a synthesizable version applicable to general systems-on-a-chip (SoC) design, and fabricated in a 90nm CMOS technology. RF power injection to power supply networks is quantified by OCM. The number of resultant erroneous bits as well as their distribution in the cell array is given by MBIST. The frequency-dependent sensitivity reflects the highly capacitive nature of densely integrated SRAM cells.

Low-frequency acoustic absorption of viscoelastic coating with various shapes of scatterers

The low-frequency underwater sound absorption phenomenon induced by the localized resonance in phononic crystal shows a promising application for the design of underwater acoustic absorption material in recently study. To further reveal the sound absorption mechanism and optimize the low-frequency underwater sound absorption characteristic, the viscoelastic coating embedded with various shapes of scatterer is investigated. In this paper, to shorten the computing time of the original finite element program and save the core memory, the conventional finite element method is simplified due to the symmetry of the lattice and the scatterers, then the simplified finite element method is validated by comparing the results of the simplified finite element method with those of the conventional finite element method. The relationship between the resonance mode described with the displacement contours of one unit cell at specified frequencies and the corresponding absorption spectrum is discussed in detail, which reveals briefly the sound absorption mechanism of the viscoelastic coating embedded with cylindrical scatterer. Finally, the shape effect of the scatterer on the sound absorption characteristics is investigated, spherical scatterers and the three cylindrical scatterers with different shapes but the same volume are considered. Further, the influence of the density of the core on acoustic absorption characteristic under an air backing is discussed. The results show that lower sound absorption properties can be deduced by adopting the cylindrical scatterers and reducing the radius of the base of circular cylindrical scatterer, and the absorption bandwidth can be improved by choosing the optimal scatterer material.

All-electrical operation of magnetic vortex core memory cell

A single vortex-core switching in a ferromagnetic disk is detected in real time by using a three-terminal device with the tunneling magnetoresistance junction. We show that the device works as a vortex core memory cell, where reading and writing can be done in an all-electrical way: binary data corresponding to the core direction can be read out electrically as the amplitude of the output, while the data can be written electrically by applying a pulsed current.

Multiple Indices of Diffusion Identifies White Matter Damage in Mild Cognitive Impairment and Alzheimer’s Disease

The study of multiple indices of diffusion, including axial (DA), radial (DR) and mean diffusion (MD), as well as fractional anisotropy (FA), enables WM damage in Alzheimer's disease (AD) to be assessed in detail. Here, tract-based spatial statistics (TBSS) were performed on scans of 40 healthy elders, 19 non-amnestic MCI (MCIna) subjects, 14 amnestic MCI (MCIa) subjects and 9 AD patients. Significantly higher DA was found in MCIna subjects compared to healthy elders in the right posterior cingulum/precuneus. Significantly higher DA was also found in MCIa subjects compared to healthy elders in the left prefrontal cortex, particularly in the forceps minor and uncinate fasciculus. In the MCIa versus MCIna comparison, significantly higher DA was found in large areas of the left prefrontal cortex. For AD patients, the overlap of FA and DR changes and the overlap of FA and MD changes were seen in temporal, parietal and frontal lobes, as well as the corpus callosum and fornix. Analysis of differences between the AD versus MCIna, and AD versus MCIa contrasts, highlighted regions that are increasingly compromised in more severe disease stages. Microstructural damage independent of gross tissue loss was widespread in later disease stages. Our findings suggest a scheme where WM damage begins in the core memory network of the temporal lobe, cingulum and prefrontal regions, and spreads beyond these regions in later stages. DA and MD indices were most sensitive at detecting early changes in MCIa.

Disrupting reconsolidation: Pharmacological and behavioral manipulations

We previously demonstrated that disrupting reconsolidation by pharmacological manipulations "deleted" the emotional expression of a fear memory in humans. If we are to target reconsolidation in patients with anxiety disorders, the disruption of reconsolidation should produce content-limited modifications. At the same time, the fear-erasing effects should not be restricted to the feared cue itself considering that fear generalization is a main characteristic of anxiety disorders. In Experiment I and Experiment I(b), we addressed these issues using a within-subject differential startle fear conditioning paradigm and a test of fear generalization. In Experiment II, we tested whether a behavioral approach targeting the reconsolidation through extinction learning was also effective in weakening the original fear memory. A behavioral procedure is evidently preferred over drug manipulations provided that similar effects can be obtained. Here, the extinction procedure subsequent to retrieval did not "erase" the emotional expression of the fear memory as the retrieval techniques (i.e., reminder shocks and reacquisition) unveiled a return of the startle fear response to the fear-relevant stimuli. In contrast, β-adrenergic receptor blockade during reconsolidation selectively deleted the fear-arousing aspects of the memory (i.e., startle fear response) along with its category-related information. The pharmacological manipulation rendered the core memory trace too weak to observe fear generalization after successful reacquisition. Hence, relearning following the disruption of reconsolidation seems to be qualitatively different from initial learning. Our findings demonstrate that disrupting reconsolidation by pharmacological manipulations, although selective, undermines the generalization of fear, a key feature of anxiety disorders.

1-Tbyte/s 1-Gbit DRAM Architecture Using 3-D Interconnect for High-Throughput Computing

Aiming to resolve memory bottlenecks in multi-core system, novel 1-Tbyte/s 1-Gbit DRAM architecture based on a multi-core configuration and 3-D interconnects was developed. The DRAM stacked on a multi-core CPU has 512-bit I/Os with through-silicon-via (TSV) distributed in 16 memory cores. Five-stage pipelined architecture in the compact DRAM core was developed to reduce the operation cycle of the data-bus to 2 ns. A low-noise early-bar-write scheme for an 8-ns cycle array operation and 16-Gbit/s I/O circuits on TSV were also developed. The proposed DRAM architecture greatly improves power efficiency. TSV scheme reduces the parasitic capacitance of the interconnects between the DRAM and CPU, and multi-core architecture reduces the length of the data bus on the DRAM. A 1-Gbit DRAM was designed based on the 45-nm stand-alone DRAM process. Chip size is 51.6 mm2 assuming 4F2 memory cells, and the density is about 5 times higher than that of embedded DRAM. Circuit simulations confirmed the 2-ns operation of the data bus, 8-ns operation of the memory array, and 16-Gbit/s operation of I/O circuits. Power consumption is 19.5 W, providing power efficiency of 51.3 Gbyte/s/W, which is an order of magnitude higher than that of conventional DRAMs.