Core Gate Research Articles

Parameteric optimization of SiGe S/D NT JLFET using analytical modeling to improve L‐BTBT induced GIDL

AbstractIn the present work, we investigate the impact of structure dimensional parameters on the short channel effects which occurs especially below 20 nm regime particularly gate induced drain leakage (GIDL) current. Using technology computer aided design simulation (TCAD), we have examined the GIDL for SiGe as source/drain in NTJLFET. The structural dimensional parameters such as the nanotube thickness, core and outer gates thickness and gate electrode work function shows the significant impact on the band to band tunneling in lateral direction (L‐BTBT) which induced GIDL current. It is analyzed that increase in the nanotube thickness and physical oxide thickness increase the GIDL current, while increasing the gate electrode work function, core gate and outer gate thicknesses gives reduced GIDL current. The SiGe S/D NTJLFET produce a remarkable high ION/IOFF ratio ~ 1011. A compact model for GIDL current is also developed which shows the dependency of structure parameters on leakage current. The SiGe has been incorporated as source and drain in NTJLFET which creates the energy band discontinuity. Furthermore, SiGe S/D NTJLFET is fairly compared with the conventional NT JLFET and nanowire (NW) JLFET and shows an improved performance.

Investigation of Gate Induced Drain Leakage in Nanotube and Nanowire: A Comprehensive Study

In this paper, a comprehensive study of gate-induced drain leakage (GIDL) in conventional silicon-nanotube (Si-NT JLFET), SiGe Source/Drain silicon-nanotube junctionless field effect transistor (S/D Si-NT JLFET) and conventional nanowire (NW) have been performed using technology computer-aided design simulations. We have also demonstrated that inclusion of SiGe S/D in Si-NT JLFET reduced the OFF-state current by order of [Formula: see text]3 from NT JLFET and by order of [Formula: see text]6 from NW JLFET. The impact of variation of core gate thickness ([Formula: see text], germanium (Ge) content [Formula: see text], and location of SiGe in source and drain regions of the S/D Si-NT JLFET have been studied from the GIDL perspective. We found that SiGe S/D Si-NT JLFET exhibits impressively high [Formula: see text]/[Formula: see text] ratio [Formula: see text]10[Formula: see text] with reduced lateral band-to-band tunneling (L-BTBT)-induced GIDL than the conventional nanowire device. The is due to SiGe S/D that creates a energy valence band discontinuity at source drain interfaces which limits the flow of electrons from channel to drain region in the OFF-state.

Design and Development of Biosensors Based on Nano Tube Tunnel Field Effect Transistor

Tunnel Field Effect Transistor (TFET) is gaining recognition and provide solution for Integrated Circuit (IC) design with low power. This is due to TFET's carrier transportation scheme, which utilizes inter-band tunneling of carriers, and its fabrication similarity to MOSFET. TFET presents itself as a widely adopted device structure that can overcome the limitations of MOSFETs. However, TFETs suffer from poor DC and Radio Frequency (RF) performance, mainlydue to minority carrier transport and physical doping, which forms an abrupt junction in nanoscale devices due to RDFs. The junction-less device structure presents a viable solution to these issues without sacrificing DC parameters, even at high-frequency. Furthermore, the nanotube structure of TFET effectively reduces the Subthreshold Swing (SS) and leakage current due to better controllability of channel. The gate-all-around structure of nanotube TFET improves the surface potential distribution over the channel region, not only enhancing the DC characteristics of TFET but also improving the high-frequency parameters. The core gate Nano Tube (NT)-TFET is a promising device structure for exploring its application in the field of biomedical science as a biosensor. The proposed core gate nanotube structure provides a larger surface area for immobilizing biomolecules in the cavity, thus improving sensitivity analysis. This work proposes the utility of a novel core gate NT-TFET as a biosensor for detecting label-free biomolecules and DNAs. In this design, the detection capability of biosensor is improved, and the detection processes are investigated by high-frequency parameters of the proposed twin cavity dual metal NT-TFET biosensor. This study demonstrates the sensitivity analysis of biosensor based on transit time and device efficiency, which are two critical high-frequency parameters. This approach results in a biosensor with a lower annealing budget, making it more cost-effective and with comparatively highersensitivity

A Vertical Single Transistor Neuron with Core-Shell Dual-Gate for Excitatory-Inhibitory Function and Tunable Firing Threshold Voltage.

A novel inhibitable and firing threshold voltage tunable vertical nanowire (NW) single transistor neuron device with core–shell dual-gate (CSDG) was realized and verified by TCAD simulation. The CSDG NW neuron is enclosed by an independently accessed shell gate and core gate to serve an excitatory–inhibitory transition and a firing threshold voltage adjustment, respectively. By utilizing the shell gate, the firing of specific neuron can be inhibited for winner-takes-all learning. It was confirmed that the independently accessed core gate can be used for adjustment of the firing threshold voltage to compensate random conductance variation before the learning and to fix inference error caused by unwanted synapse conductance change after the learning. This threshold voltage tuning can also be utilized for homeostatic function during the learning process. Furthermore, a myelination function which controls the transmission rate was obtained based on the inherent asymmetry between the source and drain in vertical NW structure. Finally, using the CSDG NW neuron device, a letter recognition test was conducted by SPICE simulation for a system-level validation. This multi-functional neuron device can contribute to construct a high-density monolithic SNN hardware combining with the previously developed vertical synapse MOSFET devices.

Gated Photodetector with a Bipolar Response from Single-Crystal Halide Perovskite Using a Polymeric Electrolyte as the Gate Dielectric

In this report, we show that a gated optical detector working in the visible wavelength region can be made on single-crystal halide perovskite methylammonium lead bromide (CH3NH3PbBr3 or MAPB). A polymeric electrolyte (PEO/LiClO4) is used as the gate dielectric, which forms an electric double layer (EDL) at the electrolyte/MAPB interface, leading to high specific gate capacitance and enabling enhanced carrier induction at a low gate bias. The photoresponse of the detector can be enhanced significantly by a large factor (e.g., by a factor of 35) by a bias Vg of 10 V. The core gate operation is due to the field effect, and the detector shows the characteristics of a field effect transistor (FET) with bipolar nature, thereby operating with both polarities of the gate bias. This is enabled by the special feature of halide perovskites, that is, they have appreciable mobility for both types of carriers. It is established that the enhancement of the detector current response occurs due to the synergy of carriers created by illumination as well as the gate when they are present simultaneously, which modifies the near-band-edge trap states close to valence band maxima (VBM) and conduction band minima (CBM) and enhances the carrier mobility. The proposed synergy mechanism is validated by the gate-induced enhancement of the photoluminescence (PL) emission intensity and narrowing of the emission line.

Design of Core Gate Silicon Nanotube RADFET with Improved Sensitivity

The prominent feature of Silicon nanotube MOSFET for using RADFET application is its high Ion/Ioff ratio, minimal leakage current and less sensitive to short channel effects. Due to the above features the radiation behaviour of the device is studied to check for the applicability of a RADFET. Here both uniform and non-uniform irradiation characteristics are analysed. The focus of this study is on electrical characteristics and sensitivity, which is measured as a variation of threshold voltage of radiated and unirradiated device. It was found that on irradiation, the surface potential variation is high for 40 nm channel length hence the analysis is conducted for the same. It was proven to be successful, as the device achieves high Ion/Ioff ratio of the order 1013 and a sensitivity of 2.26 mv Gy−1. The obtained results are compared with DG RADFET and JL DG RADFET and it shows that Core gate Silicon nanotube RADFET has better electrical characteristics and sensitivity. The simulations are performed in Silvaco 3 D Atlas TCAD simulation software.

A physics-based drain current model for Si1-xGex source/drain NT JLFET for enhanced hot carrier reliability with temperature measurement

In this paper, we report, the hot carrier reliability issue in the Si1-xGex source/drain nanotube (NT) junctionless field-effect transistor (JLFET) with temperature variations. The surface potential, electric field and drain current have been formulated by developing a physics-based analytical model. SiGe in the source/drain regions creates valence band discontinuity of ΔEg = 0.23 eV which significantly increases the tunneling width at the channel/drain interface and therefore, results in a diminished L-BTBT action. The results demonstrate that at T = 500 K, drain current with the influence of interface trap charges in the Si1-xGex S/D architecture shows better immunity than the conventional NTJLFET. The Si1-xGex S/D enhances the reliability of analog/RF parameters such as transconductance (gm), intrinsic gain (gm/gd), cut-off frequency (fT), and gain-transconductance-frequency-product (GTFP), against the hot carriers. We have also explored the reliability with germanium (Ge) content, x and observed that for Ge content above x = 0.3, the reliability degrades in terms of higher electron temperature, reduced gm, and lower fT. The analytical results are verified and are in good agreement with results of Sentaurus TCAD simulations. The Si1–xGex S/D architecture combined with NT core gate can help relieve the HCI trap charge reliability for JLFETs leading to significantly improved analog/RF parameters.

Performance Analysis of Charge Plasma Induced Graded Channel Si Nanotube

This paper investigates a comparison based on DC and AC analysis of a charge plasma-based graded channel nanotube in two configurations. Nanotube structures offer enhanced gate ctontrol over other devices, they offer higher on-current than nanowires of equivalent silicon film thickness, making them a promising device, however, the core gate of nanotube results in higher gate leakages also. This paper draws a comparison of the two possible configurations of making a graded channel without ion implantation. The results show that a gate of higher work function in S-GC-NTFET is necessary to bring the same subthreshold characteristics as D-GC-NTFET. The D configuration shows slightly enhanced DC characteristics however, the RF analysis shows better results for S configuration.

Impacts of core gate thickness and Ge content variation on the performance of Si1−xGex source/drain Si–nanotube JLFET

Impacts of core gate thickness and Ge content variation on the performance of Si1−xGex source/drain Si–nanotube JLFET

Comparative Study of Single and Double Gate All Around Cylindrical FET Structures for High-K Dielectric Materials

The performance of conventional MOSFET deteriorates because of the short channel effects that appears when it is scaled into nm regime. The existing techniques like channel scaling, variations in the work function implemented on a MOSFET could no longer confront these limitations which demand for the necessity of some upgraded devices and materials that would overcome these shortcomings and offer ameliorate performance. Two experimentally based devices gate all around (GAA) FET and double gate all around (DGAA) FET are modeled and compared at 10 nm and 20 nm respectively In this paper, the effect of scaling the gate length, oxide thickness and variations in the drain to source voltage utilizing two different gate dielectrics for a single and double GAA cylindrical FET on their respective device performance in terms of drive current (ION), leakage current (IOFF), switching speed (ION/IOFF) and subthreshold swing. The study reveals that with a thinner gate oxide, less gate length, less drain to source voltage and with an additional core gate utilizing high-k dielectric materials, the device achieves a better subthreshold slope, higher value of ON-state current, larger ON/OFF current ratio, lesser OFF-state current and lesser power consumption.

Performance Analysis of Channel and Inner Gate Engineered GAA Nanowire FET

The present paper presents a graded channel NWFET using a doping-less technique with a core gate covering the channel and drain region. The graded channel and inner gate further suppresses the short channel effects and enhances the device performance capabilities. The performance metrics of the aforementioned device are calculated and compared with Charge Plasma and junctionless GAA-NWFET. The results show that our proposed structure exhibits improved Ion, Ioff, subthreshold slope (SS) and drain induced barrier lowering (DIBL). The graded channel has been effectively created by means of the charge plasma technique inorder to decrease the fabrication cumbersomeness. To enhance the channel controllability further, using an inner gate is proposed. Our proposed device aims at making MOSFET more striking to carry on with the scaling trends.

Performance optimization of a nanotube core–shell semi-junctionless p+p+n heterojunction tunnel field effect transistor

In this paper, the electrical characteristics of a heterojunction nanotube semi-junctionless tunnel field effect transistor (NSJTFET) with germanium in the source and GaAs in the drain channel regions are thoroughly investigated. The proposed n-channel NSJTFET is a p+p+n structure, employing internal core gate and external shell gate. The device under study provides a superior gate control over the channel by amplifying the band-to-band tunneling rate. The results imply that an increased on-state drive current of nearly 100 times as compared to the conventional nanowire tunnel field effect transistor (TFET) is achieved. In addition, the steep slope NSJTFET structure exhibits subthreshold swing of approximately 7.6 mV/dec in comparison with 25 mV/dec for the conventional TFET. Sensitivity analysis of main electrical parameters demonstrates that source-channel doping concentration and metal gate workfunction are critical design parameters that may affect the device performance. Moreover, a framework of core–shell gate workfunction engineering is utilized via calculating 2D variation matrix of the on-state current, threshold voltage and off-state current for optimizing the device performance.

Junctionless Silicon Nanotube TFET for Improved DC and Radio Frequency Performance

In this work, a junctionless silicon nanotube TFET (JL-SiNT-TFET) is reported for low standby power and high-frequency applications. The workfunction of the core gate (CG) metal is considered similar to the outer gate electrode. The length of the CG is extended up to the source region and connected to the gate supply voltage. The inclusion of the CG offers better electrostatic controllability and enables a steep turn on capability. While maintaining low IOFF and targeting the optimum performance of the device, the JL-SiNT-TFET shows 19.8 mV/dec subthreshold swing (SS), ultra-low OFF-state leakage current, higher drive current as compared to the junctionless silicon nanowire TFET (JL-SiNW-TFET). However, temperature and substrate doping effect on device performance, core gate position optimization, the impact of channel length variation on SS, ION/IOFF ratio, and RF parameters are also investigated for choosing the most favorable values.

SiGe/Si hetero nanotube JLFET for improved performance: proposal and investigation

The authors report, for the first time, a novel SiGe/Si n-type hetero nanotube (HNT) junctionless field-effect transistor (JLFET), which leads to a remarkably enhanced performance below the sub-10 nm gate length. It is shown that valence band discontinuity in the HNT JLFET causes tunnelling width of the channel–drain interface to increase and therefore diminishes the lateral tunnelling of electrons in the OFF state. The impact of high-κ spacers and core gate diameter on the dynamic performance of HNT JLFET has also been studied. They show that the inclusion of high-κ spacers does not affect the dynamic performance of the HNT JLFET. It is demonstrated using calibrated 2D simulations that the proposed device exhibits a smaller value of DIBL 4 mV/V, sub-threshold slope almost 60 mV/decade, and an improved ION/IOFF ratio of ∼1012 even for sub-10 nm gate lengths.

Inner-Gate-Engineered GAA MOSFET to Enhance the Electrostatic Integrity

Gate-all-around (GAA) MOSFETs are the best multi-gate MOSFET structure due to their strong electrostatic control over the channel. The electrostatic controllability can be enhanced further by applying some gate engineering technique to the existing GAA structure. This paper investigates the effect of inner gate (core gate) on the electrostatic performance of conventional GAA MOSFET. The inner gate engineering increases both the electrostatic control and packing density of GAA MOSFET. In this paper, we have presented an inner-gate-engineered (IGE) GAA MOSFET and inspected its advantages over conventional counterparts. The proposed structure exhibits higher [Formula: see text] ratio, low threshold voltage and improved RF performances as compared to the conventional structure. Analytic simulation has been carried out for numerous figures of merit (FOMs) for different technology nodes.

A Line Tunneling Field-Effect Transistor Based on Misaligned Core–Shell Gate Architecture in Emerging Nanotube FETs

In this paper, a new architecture based on an intentional misalignment between the core and shell gate is presented for the nanotube tunnel field-effect transistor (NT-TFET). The misaligned core gate overlaps with the source region and facilitates line tunneling in the core-gate–source overlapped region significantly increasing the band-to-band tunneling (BTBT) rate. Using the calibrated 3-D simulations, we show that the proposed misaligned (MG) NT-TFET outperforms the conventional NT-TFET both in terms of static as well as dynamic performance. The MGNT-TFET exhibits an increased ON-state current by nearly 11 times as compared to the conventional NT-TFET with an ultrasteep subthreshold slope (minimum point subthreshold swing of ~5 mV/dec and an average subthreshold slope of 15.5 mV/dec). The higher effective drive current also leads to an improved dynamic performance in the MGNT-TFET

Performance investigation of steep-slope core–shell nanotube indium nitride electron–hole bilayer tunnel field effect transistor

In this paper, the effects of main physical and structural parameters on the electrical characteristics of indium nitride core–shell nanotube electron–hole bilayer tunnel field effect transistor (NEHBTFET) are comprehensively investigated via simulation study for optimizing the device performance. The proposed structure offers excellent band to band tunneling efficiency and steeper turn-on drain current by providing the tunneling junction normal to the gate electric field between the region of outer shell gate and inner core gate. The simulation results reveal that the on-state current and subthreshold swing of NEHBTFET are greatly improved via expanding the band to band tunneling area along the channel and in the vertical direction in comparison with conventional nanowire TFET with narrow lateral source–channel tunneling junction. The n+–p+ tunneling junction is created electrically in the intrinsic region and a framework of core and shell gate work function engineering are conducted via calculating 2D variation matrix of the on-state current and threshold voltage for optimizing the device performance. The sensitivity of device’s main electrical parameters with respect to the variation of device physical and geometrical parameters reveals that the electrical parameters are highly insensitive to the source doping density which solves the major challenge of low solubility of dopants in III-nitride devices. In addition, the off-state current and subthreshold swings are not affected by the gate length scaling that is an indication of feasibility of this device in nanoscale regime.

Investigation of the Scalability of Emerging Nanotube Junctionless FETs Using an Intrinsic Pocket

The detrimental lateral band-to-band tunneling (L-BTBT) governing the OFF-state performance of the junctionless (JL) FETs is more pronounced in emerging Nanotube (NT) transistor architectures. This restricts the scaling of NT JLFETs irrespective of their ultimate electrostatic gate control due to additional core gate. Therefore, in this paper, we propose a symmetric intrinsic pocketed Pi-NT JLFET which has narrow intrinsic pockets on both sides of the channel region leading to a diminished L-BTBT induced lateral parasitic BJT action in the emerging NT JLFETs. Using calibrated 3-D simulations, we demonstrate that the incorporation of an intrinsic pocket decreases the OFF-state current by around 2 orders of magnitude in the Pi-NT JLFET for a gate length of 20 nm, leading to a significant ON-state to OFF-state current ratio ( $I_{\text{ON}}/I_{\text{OFF}}$ ) of 108. Furthermore, we also show an improvement in the performance of the emerging NT junctionless accumulation mode (JAM) FETs which exhibits a degraded performance compared to NT JLFETs due to enhanced L-BTBT irrespective of their higher ON-state current. The inclusion of the intrinsic pockets in NT JAMFET (Pi-NT JAMFET) reduces the L-BTBT originated OFF-state by 3 orders of magnitude for a gate length of 20 nm leading to an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of 108. Moreover, the proposed Pi-NT JLFET and Pi-NT JAMFET exhibit an impressive $I_{\text{ON}}/I_{\text{OFF}}$ ratio of ~ 108 and 106, respectively, with more than 4 orders of remarkable reduction in the leakage current even when the gate length is scaled to 10 nm. Additionally, the proposed architectures exhibit lower sensitivity to the gate length modulation unlike their conventional counterpart. The Pi-NT transistors exhibit superior immunity against the short channel effects of threshold-voltage roll-off due to the reduced electrostatic source/channel-to-drain coupling. Furthermore, we show that incorporating gate engineering of the dual-material gate (DMG) further enhances the performance of the Pi-NT transistor. The DMG-Pi-NT transistors exhibit an enhanced $I_{\text{ON}}/I_{\text{OFF}}$ ratio ~ 1011 achievable with the proper tuning of the dual metal gate work functions. Thus, our proposed device architecture enhances the scalability of the NT JLFETs and NT JAMFETs for realizing them in the future technology nodes.

Design and performance analysis of Dual-Gate All around Core-Shell Nanotube TFET

In this research work, we have put forward Silicon based Nanotube structure with Dual Gate All around configuration. The proposed device has been compared with Conventional Nanowire structure and the comparison is concocted on account of analog parameters of both the devices. The structural parameters of both the devices are kept identical like work function, doping concentrations of Source, Channel and Drain regions. By using an inner core gate and an outer shell gate, the proposed device exhibited superior Analog characteristics over its Nanowire counterpart in terms of drive current (ION), Electrical criteria, capacitance, unity gain, and transconductance.

Wigner transport simulation of (core gate) silicon-shell nanowire transistors in cylindrical coordinates

Gate-all-around silicon nanowire transistors (SNWTs) are recognized as promising candidates to reduce problems due to quantum effects in conventional nano-transistors. In this study we investigate whether structural modification of SNWTs leads to improved performance. A model calculation for a transistor with a channel length of several nanometers requires a quantum transport simulator, and we use a Wigner transport equation (WTE) discretized by a third-order upwind differential scheme (TDS) suggested by Yamada et al. (2009) for quantum transport simulations of gate-all-around silicon-shell nanowire transistors (SSNWTs), core gate SSNWTs (CG-SSNWTs), and independent CG-SSNWTs (ICG-SSNWTs). A WTE discretized by the TDS is known to produce highly accurate results. The SSNWT has a structure in which an insulator cylinder is inserted into the center axis of the SNWT, and the CG-SSNWT has a structure in which a core gate is inserted into the center axis of the SSNWT. The calculations show that the performances of the SSNWTs are improved by introducing the Si-shell structure and the core gate. The ICG-SSNWTs are identical in structure to the CG-SSNWTs, but the outer and core gates are independently biased. The calculations for the ICG-SSNWTs show that the threshold voltage can be controlled using the difference between the core and outer gate voltages.